Proposal: CNS 0551710 PI: Harrison, Williams L. Institution: University of Illinois at Urbana-Champaign
The principal investigators will create an open hardware and software platform exploiting opportunities for convergence of computing and communications. Communications functions are being carried out by ever more sophisticated, programmable and reconfigurable devices such as signal processors, network processors, and FPGAs that process live streams of high-bandwidth data: video streams from surveillance cameras, live transactions flowing over the internet, and physical data collected by sensor. These streams often call for intensive, real-time computation.
This project, the ILLIAC 6, will create an open platform an infrastructure in hardware and software -- for integrated high-performance communications and supercomputing. The project is a collaboration among the University of Illinois at Urbana-Champaign, Analog Devices Incorporated, and Mentor Graphics, with contributions and support from several other companies. The central components are high-performance low-power communications processors and FPGAs with multi-gigabit serial transceivers. The platform is designed to be scaled through five levels of packaging: mezzanine card, carrier board, chassis, subsystem, and system. Under this award, the mezzanine card and carrier boards will be designed, simulated (physically and logically), manufactured, and demonstrated using several applications, from the domains of software radio and image processing. The chassis will be designed and simulated (for signal integrity, thermal relief, and logical function).
The firmware / software side of the project will be a lightweight kernel that resides on the processors, the implementation of the interconnect and support for reconfigurable logic in the FPGA fabric, and a program mapper that implements the programming model for the system. The programming model is based on components that communicate via streams. The programming model is a guaranteed bandwidth model. Applications specify bandwidth requirements on their input and output streams. The program mapper is responsible for translating these application-level bandwidth requirements into requirements on individual components, and for mapping components onto the computational and communication resources of the system so as to achieve the targeted bandwidths. The hardware of the system and the programming model are co-designed to ensure that bandwidth determinism is guaranteed from the top to the bottom of the system.
