This project, acquiring an extremely low-latency multiprocessor system with on-board hardware accelerators, develops efficient scalable algorithms and software resource management schemes for individual applications. The cluster will be used in support of the following projects.
-Investigation into scalable hardware and software design for Internet web servers and data centers, -Symbolic model checking, -Pattern discovery for biological applications, -Automatic compilation of high-level code, such as C or Fortran, into RTL VHDL code, -Warp processing, and -Augmenting existing microarchitecture with security protections ensuring integrity & confidentiality of program execution.
The proposed cluster can be partitioned into several subclusters that can work independently and simultaneously on different applications, provides ultra low message passing latency within a sub-cluster and between sub-clusters, and provides an SMP environment with processors that can be used for tightly-coupled codes; thus a hybrid programming model suits different applications. The research projects on FPGA compilation, hardware/software partitioning, and CPU micro architecture design require an FPGA-based system for a test bed.
