The industry-wide transition to chip multiprocessors (multicores) means that the utility of future computer systems depends on developing effective concurrent programming methods. Transactional memory (TM) is one promising approach to this problem. Software TM (STM) implementations demonstrate TM's potential and enable early deployment, while Hardware TMs (HTMs) promise higher performance across a broader range of languages and applications.
This goal of this project is to advance the interaction of HTM technology with the large existing investment in system software. First, as a foundation, it deconstructs HTMs into mechanisms with interchangable implementations. Second, it refines these mechanisms to cohabit with existing and future language runtimes, I/O systems, operating systems and hypervisors. Third, it develops technologies for large, long-running transactions, broadening TM's applicability. Fourth, it explores applications of HTM mechanisms to other purposes, such as improving reliability, correctness, security, and performance. Fifth, it develops evaluation platforms for the required software and hardware.
The project will result in HTM designs that support advanced system software architectures, including virtualization and I/O, and simplify parallel programming through efficient long-running transactions. Additionally, these HTM mechanisms will be designed to support alternative uses that further simplify or improve software. Moreover, the project seeks a broader impact via multidisciplinary training for supported students and influence on the computer industry through industrial affiliates meetings, talks, papers, etc. Finally, it advances the GPL-released General Execution-driven Multiprocessor Simulation (GEMS) so that other researchers can leverage the evaluation infrastructure the project develops.
