Despite consumer demand for sleek, lightweight electronics, mobile embedded systems often use bulky discrete voltage regulation components to deliver noise-free power. Dedicated motherboard-level regulators increase the form factor of portable electronics. This project is developing a novel paradigm in which power regulation circuitry is designed synergistically with the computational elements of system, thereby reducing or eliminating the need for off-chip regulation. The focal point of the research is the development of models, design methodologies, and management techniques that allow low power high-performance SoCs to be directly connected to an energy source, enabling the next step in system integration.
The project seeks to develop integrated, programmable, on-chip switching regulators that leverage novel packaging technology to provide noise free supply voltages at high-efficiency. In addition, on-chip regulation improves the feasibility of fine-grained voltage domains. The project examines unique cross-boundary system optimizations spanning both software-level task management and regulation hardware design. It is developing integrated operating system and hardware methods to limit peak current, improve slew rate demands, and reduce voltage ripples through balanced scheduling. In special cases, it may be possible to completely remove regulation circuitry and allow the operating system to adapt computation under ""deregulated""gradually declining battery voltages.
The removal of dedicated off-chip regulation from embedded systems has broad potential for commercial and social impact by enabling new generations of compact, reliable embedded devices, such as consumer electronics and medical devices. This project provides educational benefits through training of graduate students and incorporation of resulting advanced material in courses.
David Brooks and Gu-Yeon Wei Harvard University Despite consumer demand for sleek, lightweight electronics, mobile embedded systems rely on bulky discrete voltage regulation components. Although effective at converting raw battery voltages to the values required for processors, dedicated board-level regulators limit device form factor from getting smaller. Given these constraints, this project investigated a novel paradigm designing power regulation circuitry synergistically with the computational elements of the system. More specifically, this project replaced dedicated off-chip regulation with cooperative on-chip hardware and software management to provide operational benefits. In practice, this allows low-power high- performance SoCs to be directly connected to an energy source while improving overall energy efficiency. The removal of dedicated off-chip regulation from high-performance embedded systems has broad commercial and societal impacts, enabling a new generation of sleek consumer, industrial, and medical devices. This market segment is valued by hundreds of millions of Americans and is critical to the continued international competitiveness of the United States, as indicated by the global market size of over a trillion dollars per year. The electricity used in everyday life is generated in remote power plants and delivered across the country to houses. Similarly, in mobile handsets, power needs to be delivered from the battery to a variety of chips required for user activities such as making calls, listening to music, and playing videos. The current way of delivering power is inefficient; it loses significant amount of power on the way to the chips and occupies a lot of space, reducing the battery life and making the handset bulky. Technology developed through this project changes the way power is delivered from the battery to chips. Just as electricity is delivered at very high voltages cross-country and reduced to 110V near our houses, our technology delivers power at a high voltage and then reduces the voltage inside the chips that use the power. This is possible owing to a tiny voltage converter that is small enough to be placed inside chips. High voltage power delivery and tiny integrated voltage regulators together enable thinner, lighter handsets with longer battery life. Showing potential for commercialization, this technology has attracted interest from major companies including Apple, Qualcomm, and AMD. This work was also invited to the University Research & Entrepreneurship Symposium, receiving interest from venture capitalists searching for disruptive technologies. Based on this feedback, there is commercialization potential for this technology upon completion of the project. There are three notable outcomes from this project: Architectural exploration of fast, per-core DVFS showed that despite the intrinsically lower conversion efficiency of integrated on-chip voltage regulators, fast conversion with multiple voltage domains enables higher overall energy efficiency. A thorough architectural study was performed for a four-core SoC embedded system across a range of traditional CPU workloads. Integrated 3-level converter is a variant of the traditional buck converter, which has attributes suited for full on-chip integration. It combines the attributes of traditional switch capacitor and buck converters. Although the 3-level converter retains an inductor, higher effective switching frequency and lower voltage swings allow for much smaller inductors that can be integrated on the die along with the rest of the converter circuitry. Compared to switch capacitor converters, the 3-level converter does not suffer a linear efficiency loss profile and is able to regulate the output voltage across a wider range and higher efficiency. A test-chip prototype implemented in a 130nm CMOS technology demonstrated peak conversion efficiency up to 80%. Integrating all components required by the 3-level converter on the die eliminates board area and allows for smaller form factors at comparable overall system energy efficiency. Fast feed-forward load compensation was added to the output of the 3-level converter to deal with sudden fluctuations in the load, which lies outside the bandwidth of the voltage regulator’s control loop. Test-chip measurements demonstrate predictive load compensation can reduce voltage droops from greater than 11% to less than 5%. The above outcomes demonstrate the value of collaborative computer architecture and IC research, which has been gaining more attention by researchers in recent years. IC technology has been maturing, but continues to present new challenges. It has become important for researchers in related, but traditionally separate fields to join forces and find holistic solutions that can continue to improve computer performance.
