Current software design for safety-critical embedded systems requires stringent compliance with coding standards to ensure safety and reliability. A key additional requirement for real-time embedded systems is predictable timing behavior of software components, which requires that bounds on the worst-case execution time (WCET) of embedded software be determined. While static timing analysis yields verifiable bounds on the WCET, it cannot keep pace with architectural innovations and hardware performance variation due to chip fabrication scaling.
This work contributes a fundamentally new approach to bounding the WCET with three major contributions: (1) Instead of simulating execution, actual execution in hardware is promoted to assess the WCET of a task. This approach not only renders tedious hardware modeling unnecessary but also confirms correct behavior regardless of architectural complexity or hardware variation. (2) The approach and its complexity are evaluated by FPGA synthesis. This assesses the feasibility of the design and validates a prototype implementation. (3) The impact of advanced architectural features is studied in a co-design space exploration, aimed to provide predictability and tight WCET bounds. The research conducted in this project advances existing science and technology through novel techniques in hardware and software design for safety-critical embedded real-time systems by providing high-confidence bounds on execution times; enhancing hardware architectures with support to assess execution times; and customizing hardware features via co-design to improve predictability. These capabilities directly benefit safety and reliability of software controlling, for example, aircraft and components of cars, thereby aiding the high-confidence design of embedded systems.
