With the demand for high memory performance from multi-core processors, memory subsystem has become a new thermal concern after processor and hard drive. Smooth and efficient memory thermal management schemes must be developed to meet the challenge. There also lack memory thermal models and simulation tools in the public domain for research and education. This project proposes memory thermal models and thermal simulators for DRAM memory subsystems as well as efficient DTM (dynamic thermal management) methods. The investigators develop a simple and accurate dynamic thermal model based on fully buffered DIMM and an accurate and fast two-level simulator estimating the thermal behavior of a memory subsystem. They also study several new, system-level DTM schemes that coordinate DRAM thermal management with processor performance throttling. Several new DTM methods are to be developed. The first method, Adaptive Core Gating, adjusts the number of active cores according to the memory thermal status. The second method, Coordinated DVFS (dynamic voltage and frequency scaling), proactively scales down the processor frequency and voltage upon memory thermal emergency, reducing both the DRAM heat generation and the processor power consumption. Furthermore, thermal-aware OS job scheduling smoothes memory traffic and DRAM heat generation by mixing jobs with different memory demands appropriately. The thermal model is validated to execution on hardware platforms; and the proposed methods are evaluated on real systems.
