This project is motivated by two recently emerged challenges in design of computer systems---the escalating temperature and the dramatically increased leakage power consumption in IC circuits---that threaten to handicap future generations of computing systems. The temperature of a computer chip increases in tandem with rapidly growing power consumption. At the same time, high chip temperature drastically increases leakage power, which is becoming a major component in the overall power consumption in today?s sub-micron IC circuits. This positive feedback loop between temperature and leakage exacerbates the design challenge, not only the power/energy minimization problem but also the temperature-constrained design problem.
This research seeks to address the temperature and power/energy consumption problem using real-time scheduling techniques, with a focus on the interplay between temperature and leakage power consumption. This project studies system-level thermal models that can capture the temperature-leakage interdependency with high accuracy while remaining simple enough for formal system level analysis. The research seeks to develop and validate novel and effective real-time scheduling techniques under both single and multiple processor platforms.
This research has the potential for significant societal impact, mitigating a critical barrier to the evolution of real-time embedded computing systems to sub-micron scales. This research yields techniques for reducing energy consumption and enhancing reliability and lifetime of computer systems (hence reducing cost and increasing dependability). The system-level models and techniques developed in this project will not only benefit computer scientists and researchers but those from many other disciplines and research domains as well. Furthermore, this project provides abundant research topics and learning opportunities for both undergraduate and graduate students. The project seeks to broaden opportunities for participation in research through outreach to recruit students from groups currently underrepresented in this field.
For the past several decades, we have experienced the tremendous improvement of computer applications and systems, thanks largely to the remarkable advancement of semiconductor technology that can integrate more and more transistors into a single IC chip. From the cell phone to the medical instrument, from the engine control for a car to the security system in our home, these computer chips have profoundly changed our way of life. However, as more and more transistors integrated into a single chip, the dramatically increasing transistor density and power consumption have presented two challenging problems that threaten to handicap the future computer systems: how to provide enough power supply and how to deal with the heat generated by the system. The goal of this project is to developed system level design techniques and analytical methods to address the power and thermal challenges in design of computing systems, with an emphasis on the interdependency of the leakage power consumption and thermal conditions. In this project, PI and the research team have made a number of important contributions: We identified and formally proved a number of general principles and guidelines on thermal aware scheduling techniques. These include: (1) To complete the same workload within an interval, using the lowest constant speed for a single processor is not always the optimal method to reduce its peak temperature, when leakage/temperature dependency is taken into considerations; (2) Similarly, using two closest neighboring speed levels does not necessarily minimize the peak temperature within an interval either; (3) To complete the same workload periodically, the lowest constant speed is the optimal schedule to minimize the peak temperature when the processor temperature reaches its stable status; (4) Under the same assumption, using two neighboring speeds is the optimal solution to optimize the peak temperature at the stable status if the lowest constant speed is not available; (5) For both single core and multi-core platforms, the peak temperature at the stable status is independent to the initial temperature; (6) For multi-core platforms, the peak temperature does not necessarily occur at the scheduling points (it may occur within a constant speed interval). We developed a series of analysis methods that are critical power/thermal aware analysis with leakage/temperature dependency taken into considerations. This includes: (1) For a periodic schedule on either single processor or multi-core platforms, we found that temperature variations at the same time of different periods follow a geometric series sequence. This enables us to formulate the temperature dynamics for periodic schedules quickly; (2) For both single processor and multi-core platform, we have developed an analytical formulation to calculate the overall energy consumption, which can speed up the energy consumption computation by two orders of magnitude in our simulation study; (3) We have developed a very efficient method to detect the peak temperature for a given voltage schedule on multi-core platforms: (4) We have developed new feasibility checking methods to quickly check if a periodic schedule can satisfy the peak temperature constraints. We have developed a series of leakage conscious thermal/power aware real-time scheduling algorithms. These algorithms vary by their underlying architectures (i.e. single or multi-core platforms), their task models (i.e. frame-based real-time tasks or periodic tasks), implementation styles (i.e. on-line/off-line) and their optimization goals (e.g. overall energy consumption reduction, system utilization, throughput maximization, reliability enhancement and peak temperature minimization.) We have developed both practical and simulation test platforms to evaluate our theoretical results. Besides the traditional synthetic simulation study, we have also built two test platforms, one is a simulation platform that integrates the architecture level simulation tools including HotSpot, Wattch, and SimpleScalar. The other one is a practical testbed based on an Intel desktop computer with multi-core processors. Throughout the entire course of this project, total seven graduate students and eight undergraduate students participated the research activities for this project. Four Ph.D students and two M.S students were graduated with degrees. Among the eight undergraduate students, five of them were supported by the REU supplement for the project, and all of them are from the underrepresented group (women or minority). Based on research from this project, we have 8 journal papers and 19 peer-reviewed conference papers published/accepted. PI also has developed a new undergraduate level course: "Embedded System Design," and two new graduate level courses: "Real-Time Systems and Applications," and "Power Aware Computing."
