Testing represents one of the major manufacturing costs in the semiconductor industry. Designing circuits with testability features significantly reduces testing costs and time. Thus, it is important for designers to be exposed to the concepts in testing which can help them design better and reliable products. In this collaborative project between the University of Toledo (UT) and Ohio Northern University (ONU), a "Digital/VLSI Test and Reliable Computing Research Laboratory" is being established for the development of computationally intensive algorithms and use of commercial CAD tools for testing digital, VLSI, and advanced semiconductor devices.
Some of the research projects being carried out include: Novel Testing Techniques for Quantum Cellular Automata (QCA) circuits; Built In Self Test (BIST) for Embedded SRAMS in System on Chips; Testing Look-Up-Table (LUT) Delay Aliasing Faults in SRAM Based FPGAs Using Half-Frequencies; Analysis and Testing of Electromigration Failures; Testing and Modeling Soft Errors in FPGAs; Reliability Analysis and Device Failures in Advanced Semiconductor Devices; Reliability Issues Related to Power Consumption in VLSI Chips during Test; and Small Delay Defects and Test Generation.
Educational modules developed from the research carried out in this project are integrated into a number of graduate and undergraduate courses at ONU and UT. Since applications of semiconductor chips are far and wide, many different industries including auto, aerospace, defense and healthcare may benefit from this project.
The major goal of the research was to establish a Digital/VLSI test and reliable computing research infrastructure to facilitate research in the area of testing, hardware security, FPGAs, and Quantum-Dot Cellular Automata (QCA). The research lab was successfully established and used by students and the PI of the grant. As a result, a number of conference papers, book chapters, and theses were published. About 15 students worked in this lab. The research lab consisting of computers, server, and software was successfully established as per target dates. 50 FPGA boards were also purchased for studying delay testing and Physical Unclonable Functions (PUFs) for hardware security. Some of the research outcomes are briefly described below: Title: Asynchronous Logic FPGA based PUF The research work is a novel approach towards Field Programmable Gate Array (FPGA) based Physical Unclonable Function (PUF) design using asynchronous logic in the field of FPGA authentication and cryptography. Title: Frequency Uniqueness in Physical Unclonable Functions. Hardware security in Field Programmable Gate Arrays (FPGAs) which use Physically Unclonable Functions (PUFs) rely on the ability to produce a large number of unique frequencies. This work will be of great benefit in preventing security threats and detecting counterfeit electronic chips.. Title: Comprehensive Techniques for Majority/Minority Logic Synthesis During the past few decades, the semiconductor industry kept pace with Moore’s Law by scaling down the feature size of Complementary Metal-Oxide Semiconductor (CMOS) technology. However, this trend is encountering serious challenges as the fundamental physical limits of CMOS is approaching and further scaling is not possible. Fortunately, with the fast development of semiconductor material and devices, many new nanostructures have been created, such as Quantum-dot Cellular Automata (QCA), Single Electron Tunneling (SET) and Tunneling Phase Logic (TPL). Of these, QCA uses majority logic, SET uses both majority and minority logic, and TPL uses minority logic. In our research, we have developed an efficient algorithm to find the minimal majority gate mapping. Our software can be used to efficiently design nanoelectronic circuits for the next generation. Title: BIST Based Test and Diagnosis of LUTs in a Virtex-4 FPGA In this work, we have designed a technique which will be used to self test the chip without the need of any external hardware. We also developed a FPGA based smart meter for use in smart grids. This smart meter is likely to be much cheaper and more secure than current smart meters.
