Testing represents one of the major manufacturing costs in the semiconductor industry. Designing circuits with testability features significantly reduces testing costs and time. Thus, it is important for designers to be exposed to the concepts in testing which can help them design better and reliable products. In this collaborative project between the University of Toledo (UT) and Ohio Northern University (ONU), a "Digital/VLSI Test and Reliable Computing Research Laboratory" is being established for the development of computationally intensive algorithms and use of commercial CAD tools for testing digital, VLSI, and advanced semiconductor devices.
Some of the research projects being carried out include: Novel Testing Techniques for Quantum Cellular Automata (QCA) circuits; Built In Self Test (BIST) for Embedded SRAMS in System on Chips; Testing Look-Up-Table (LUT) Delay Aliasing Faults in SRAM Based FPGAs Using Half-Frequencies; Analysis and Testing of Electromigration Failures; Testing and Modeling Soft Errors in FPGAs; Reliability Analysis and Device Failures in Advanced Semiconductor Devices; Reliability Issues Related to Power Consumption in VLSI Chips during Test; and Small Delay Defects and Test Generation.
Educational modules developed from the research carried out in this project are integrated into a number of graduate and undergraduate courses at ONU and UT. Since applications of semiconductor chips are far and wide, many different industries including auto, aerospace, defense and healthcare may benefit from this project.
The major objective of the proposed work was to establish computing infrastructure to perform research in the areas of testing and reliability of electronic circuits and systems. To date, the research work resulted in an accepted journal paper, 2 book chapters, and fourteen conference proceeding publications. In addition to the PI, four undergraduate students have participated in research activities until now. Some of the research outcomes are detailed below: Built-in self-test of digital systems i. A new scheme is developed to implement configurable two dimensional linear feedback shift registers to generate built-in self-test patterns for hardware logic cores implemented in integrated circuits. The hardware used 30% less number of transistors in implementation of configuration network. ii. Modular and area-efficient hardware techniques are used to detect potential electromigration failure in FPGAs and to improve their reliability. Electromigration fault signatures for short, medium, and long interconnects in FPGAs based on Arithmetic Fourier Transform coefficients was developed. iii. A two-step technique is developed to identify a developing lifetime fault and reroute its signal path using redundant resources present in the FPGA using delay faults. Nanoelectronic Circuit Synthesis A majority gate based synthesis methodology was developed that is significantly better than all existing procedures. Majority gates are the logic gates of implementation choice in many future nanoelectronic technologies such as quantum-dot cellular automata, single electron tunneling and tunneling-phase logic. In addition, a number of theoretical observations were made in the synthesis of four-variable majority and minority logic functions. Modeling Photovoltaic Circuits and Systems Photovoltaic systems were modeled using circuit level representations and new methods are proposed to improve the performance of solar modules and arrays in the presence of partial shading. In addition, theoretical and simulation studies of new topologies of dc-dc converters are proposed.
