Power consumption imposes significant design constraints across the entire spectrum of computing, from the smallest handheld device to the largest data center. New technology nodes provide significant size reduction advantages, but introduce significant challenges in the power and process variability domain. These new technology nodes introduce concerns in the available first-order models commonly used by the research community. Transistor-level and gate-level simulators can offer higher accuracy, but are too slow to model multicore processors running real programs.
Fundamentally, validating novel power-centric ideas is limited by our ability to anticipate the future and to model large-scale effects or relatively poorly understood phenomenon. Fabricating prototypes can bridge the gap, but prototype-based architecture research requires a considerable amount of complex infrastructure making it relatively rare for academic researchers. This projects proposes a complete prototyping platform, that will greatly reduce the cost and effort required for prototype-based research into power-centric multicore architectures.
