Power consumption imposes significant design constraints across the entire spectrum of computing, from the smallest handheld device to the largest data center. New technology nodes provide significant size reduction advantages, but introduce significant challenges in the power and process variability domain. These new technology nodes introduce concerns in the available first-order models commonly used by the research community. Transistor-level and gate-level simulators can offer higher accuracy, but are too slow to model multicore processors running real programs.
Fundamentally, validating novel power-centric ideas is limited by our ability to anticipate the future and to model large-scale effects or relatively poorly understood phenomenon. Fabricating prototypes can bridge the gap, but prototype-based architecture research requires a considerable amount of complex infrastructure making it relatively rare for academic researchers. This projects proposes a complete prototyping platform, that will greatly reduce the cost and effort required for prototype-based research into power-centric multicore architectures.
Computing devices over the past ten years have been increasingly focused on energy-efficient. Productivity gains in society are increasingly linked to mobile computing and new deeply embedded devices. The work in this project seeks to build infrastructure that allows research prototyping of these kinds of systems. Specifically, we have constructed detailed designs for on-chip clock sources and integrated voltage regulators that are key building blocks of future energy-optimized multicore chips. We have measured the energy efficiency of these designs in several new application domains. Furthermore, we are using these chips to help validate models that can be used for a variety of design tasks. These models are generally applicable to a range of projects including those within the Harvard VLSI/Computer Architecture research laboratory and beyond. The intellectual merit outcome of this project has been to develop a set of new prototyping technologies for energy-efficient design of multicore systems. Specifically, we have prototyped on-chip clock sources and integrated voltage regulators. These technologies could be used by other groups, and have been used in multiple designs within our laboratory. The broader impact outcome of this project has been to train several graduate students in chip design and testing. This experience is an integral part of the PhD training process for these students. We expect that these students will heavily rely on this training for their future careers. Finally, the technologies that we developed are highly relevant to industry efforts to develop energy-efficient computing technology leading to high possibility of technology transfer in the long term.
