The Network-on-chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multi-core chips. However, with growing levels of integration traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional metal/dielectric based interconnects. The wireless NoC (WiNoC) simultaneously addresses the latency, power consumption and interconnect routing problems of conventional NoCs by replacing multi-hop wired links with high-bandwidth single-hop long-range wireless channels. Recent investigations have characterized silicon integrated on-chip antennas operating in the millimeter (mm)-wave range of 50-110 GHz, and this is now a viable technology. Coupled with significant advances in mm-wave transceiver design, this development opens up new research opportunities for WiNoCs. Successful execution of WiNoC research is possible if simulation-based feasibility studies are combined with suitable prototype development. For accurate performance evaluation and characterization of mm-wave transceiver circuits and on-chip antennas, high frequency network and spectrum analyzers, signal generators, a bit error rate tester and mm-wave on-wafer probe stations are required. To complement these research efforts, the acquired equipment will be integrated into a laboratory to support undergraduate and graduate courses in multi-core architectures, mm-wave circuits and communication systems at the Washington State University and the University of Idaho. These courses will provide students with essential hands-on training with industrial grade test and measurement tools. Eventually, this training will produce a cadre of well-trained B.S., M.S. and Ph.D. graduates who will benefit both industry and academia.
This proposal aims to create a new state-of-the-art laboratory at WSU’s school of EECS, consisting of mm-wave test and measurement instruments. The principal goal of the proposed laboratory is to enhance the research outcomes of the on-going WiNoCs for multi-core systems project. Multi-core processing platforms have emerged to fulfill the performance need for many real life applications. For example, Intel’s latest 80-core prototype platform is designed to achieve unprecedented performance in multiple crucial application domains, such as graphics, financial and scientific modeling. Tilera’s multi-core processors are designed to achieve unprecedented performance in networking, multimedia and wireless infrastructure applications . All of these diverse applications will benefit from the on-chip low latency, low power communication infrastructure proposed in this work. The proposed research infrastructure advances discovery while promoting teaching and learning. Integration of research with education have been accomplished through motivation and improved training of undergraduate and graduate students. Graduate students working with the PIs extensively use the procured instruments in order to complement their research investigations with design and implementation of practical circuits and systems. Incorporating hands-on design projects using the procured instruments significantly enhanced a suite of courses. The aim is to spark students’ interest in multi-core SoC design, mm-wave circuit design, and wireless communications through practical hands-on learning experiences, and to motivate them to join these challenging fields. The objective of this proposal was to acquire test and measurement equipment to enable comprehensive investigations into wireless Networks-on-Chip (WiNoCs) as communication backbones for multi-core systems. The acquired equipment will be used to create a new state-of-the-art laboratory at the School of Electrical Engineering and Computer Science (EECS), Washington State University (WSU). The new laboratory will significantly enhance the quality of research output of the ongoing on-chip wireless communication network project. The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multi-hop communications, wherein the data transfer between two distant blocks causes high latency and power consumption. Different revolutionary approaches like optical interconnects, on-chip multi-band RF transmission lines (RF-I) and wireless interconnects with CMOS ultra wide band (UWB) technology have been explored. The photonic and RF NoCs can insert single-hop communication links between distant cores and thereby significantly reduce latency and power dissipation. However, photonic links must overcome significant technological and manufacturing challenges to become viable for mass production. Though NoCs with RF interconnects can be built using existing CMOS technology, they require long on-chip transmission lines that serve as wave guides. Wireless interconnect with UWB technology requires multi-hop communication through the on-chip wireless channels due to its short range. We are currently developing a WiNoC operating in the mm-wave frequency range using existing CMOS technology; it reduces latency and power dissipation by replacing multi-hop wired links with high-bandwidth single-hop long-range wireless channels, and eliminates the need to lay long wires across the chip. Recent investigations have characterized silicon integrated on-chip antennas operating in the millimeter (mm)-wave range of a few tens to one hundred GHz, and this is now a viable technology. Coupled with significant advances in mm-wave transceiver design, this technology opens up new research opportunities for WiNoCs. WiNoCs present unique opportunities and challenges that need to be investigated in order to bring the technology into the mainstream. Successful execution of the proposed research is possible if simulation-based feasibility studies are complemented by suitable prototype development. Through this proposal the PIs acquired mm-wave test and measurement instruments that enable design, implementation, testing and demonstration of WiNoCs employing mm-wave transceivers and on-chip antennas.
