As technology scales to 10nm, CMOS-based memory devices may no longer be the technology of choice. Instead, emerging technologies, such as phase-change memory, spin-transfer torque magnetic memory, and ferromagnetic memory, are more scalable and are viable alternatives for the post-silicon era. These memory devices are diverse in their physical operation and performance and there is no winner-takes-all! This project advocates the use of heterogeneous memory systems which combine the advantages of the different memory technologies to deliver superior system performance.
The first step involves development of a hierarchical memory model which captures both the generic behavior and unique device physics of the different memory technologies. This model is also capable of predicting the performance and reliability of future technology nodes. The next step is on integration of this model into circuit and architecture-level simulators for exploration of heterogeneous memory systems. The intellectual merit lies in the coordinated effort spanning from device physics to modeling to architecture exploration. Research advances will be made in memory device modeling including predictive modeling, error analysis and modeling, error management for improved reliability and heterogeneous memory system design. The research outcome from this project is expected to have a significant impact on integrated circuit design industry and national economy. The proposed effort will foster a unique environment for multi-disciplinary research and training. It will help bridge the gap between memory device physics and computer architects by training undergraduate and graduate students in cross-disciplinary research and also by providing an open simulation environment for exploratory memory design.
