The complexity and power demands for System-on-Chips are projected to grow in coming years, making low-power design and low-loss power delivery critical for power-efficiency of future embedded systems. The objective of the proposed research is to explore innovative technology and methodologies for effective power management in embedded processors considering the interdependence between power delivery and low-power design. A system platform is being developed in which the power management unit, consisting of the power delivery and the power control circuits, is integrated vertically with a processor using 3D heterogeneous integration. An integrated approach is pursued that couples the circuit innovations in the 3D power management tier with the on-line control of the processor power to maximize the power-efficiency of the system while ensuring reliable operation.
Embedded systems are ubiquitous in modern society in various applications including medical systems, handheld devices, aviation systems, networking, and security, to name a few. Power management is often considered to be the most critical problem for future embedded systems. The 3D approach to power management can enable transformative solutions to the power problem in embedded systems, removing barriers to major advancements in their power-performance, relaxing packaging constraints, and reducing system footprint. The research results are disseminated through conference and journal publications, short-courses, tutorials, and project website and integrated in the graduate and undergraduate VLSI courses. The project is engaged with the Summer Undergraduate Research in Engineering/Science (SURE) and Facilitating Academic Careers in Engineering and Science (FACES) programs to increase participation of undergraduate and under-represented students in computer systems research.
