Silicon physically unclonable function (PUF) is a supplemental circuit embedded in an IC which generates signatures unique to its native IC. This signature could be used for authentication, protection of data and secure communication. PUFs rely on the presence of uncontrollable variations in the fabrication process causing the circuit parameters to exhibit randomness. Current approaches for PUF design have mostly investigated circuit and architectural aspects. PUF quality is severely marred by a lack of understanding of exactly how fabrication process variations impact the PUF responses. Much of the existing work assumes the fabrication process to be a black box. This results in several opportunities being unutilized. This research investigates fundamentally different approaches to PUF enhancements. It leverages quantified models for fabrication randomness that have been developed in Design for Manufacturability related research endeavors. This research looks into mask, circuit and layout level techniques along with their interdependence.
This work enables improved silicon PUFs thereby increasing the possibility of their adoption. Our approaches would be useful for both semiconductor manufacturing companies and fab-less design houses. On an education front, PhD students shall be involved in the core aspect of this work while undergraduates shall be used for data collection, analysis and test-bed development. Lastly, this project plans to enhance infrastructure for research and education by making available all the artifacts produced by this research in public domain. Further outreach efforts such as tutorials, panel discussions, etc. shall also be organized.
