To reduce production cost while meeting time-to-market constraints, semiconductor companies usually design hardware systems with reusable hardware modules, popularly known as Intellectual Property (IP) blocks. Growing reliance on these hardware IPs, often gathered from untrusted third-party vendors, severely affects the security and trustworthiness of the final system. The hardware IPs acquired from external sources may come with deliberate malicious implants, undocumented interfaces working as hidden backdoor, or other integrity issues. Tampered hardware IPs can lead to security and privacy concerns (e.g., when used in handheld devices) as well as life-threatening consequences (e.g., when used in safety-critical systems). It is extremely difficult to verify the integrity and trustworthiness of hardware IPs due to incomplete functional specifications and lack of golden reference models. To address this critical need, in this project, we develop a comprehensive and scalable framework for IP trust analysis and verification. We evaluate IPs of diverse types and forms and develop threat models, taxonomy and instances of IP trust/integrity issues. We investigate an integrative IP trust validation framework that combines the complementary abilities of functional, structural and parametric verification. We employ both statistical as well as judicious directed tests to sensitize rarely triggered malicious changes and observe their effects. The unified validation framework is flexible to detect diverse tampering efforts, scalable to large designs, and eliminates the need for a golden model. A platform for IP trust validation, threat analysis, and trust metrics would provide enabling technology to future designers to implement secure and trusted systems for diverse applications.
