Investigators from two groups at the University of California at Riverside (UCR) and one group at Nanjing University, China, develop materials technologies necessary for realizing the scalability of flash memory technology toward the CMOS ultimate limit and beyond using ordered Ge/Si core-shell quantum dots. Flash memory, which is a key component in many portable electronics, will not operate properly when higher storage capacity and lower power consumption are requested. As an alternative device, silicon nanocrystal memory, although being extensively investigated by the memory industry for commercialization, will also fail for technology nodes beyond 32nm. The key issues are non-uniform writing and erasing due to floating dot density variation and unacceptable short retention as a result of thinner tunnel oxide for lower voltage operation. In this project, engineering of Ge/Si core-shell quantum dots into one-dimensional arrays through cooperative self-assembly is synergistic with the current CMOS scaling trend toward one-dimensional structures and is expected to result in additional performance improvement. The effect of scaling on the electronic properties of the Ge/Si core-shell quantum dots is theoretically investigated using fully atomistic models and both semi-empirical and first-principle models. Experimental fabrication and characterization provide close coupling between the theory and experimental data.
Summer exchange activities and small workshops of research presentations allow participating PhD students and undergraduate students to be trained in a wide variety of areas of expertise. Research-based curriculum development, web-based dissemination of research results, publications and conference presentations, and dissemination to local school districts through videos will impact more students including those at the pre-college level. Considering the very diverse background of student body in UCR and its surrounding area, many of the students involved and affected come from groups traditionally underrepresented in science and engineering. This international exchange of students exposes U.S. students to the Chinese style of networking in research and Chinese culture in Nanjing, and it also exposes Chinese students to U.S.-style research and culture. If successfully demonstrated, the work will have broad impact on the nonvolatile memory industry. This project is co-funded by the Division of Materials Research, the Office of International Science and Engineering, and the MPS Directorate Office of Multidisciplinary activities.
Flash memory, which is a key component in many portable electronics such as tablets, cell phones, digital cameras, employs a continuous polycrystalline silicon layer in the dielectric layer of a field effect transistor to store charge and realize memory functionalities. Nanocrystal memory using discrete nanocrystals instead of continuous film as floating gate was proposed as an alternative to traditional flash memory for improved memory properties because of the discrete nature of the charge storage nodes. With memory feature size shrinking down, dot density fluctuations from cell to cell, high leakage, etc impose serious constraints on overall chip performance. To alleviate these issues, in this Materials World Network project, the researchers from UC Riverside and Nanjing University, China worked on new nanostructures and devices to extend the nanocrystal memory scaling limit. First, germanium/silicon core-shell hetero-nanocrystals were used as floating gates for nonvolatile memory application. The nanocrystals were fabricated by germanium selective growth on silicon nanocrystals in a chemical vapor deposition system. Metal-oxide-semiconductor field effect transistor memory with germanium/silicon hetero-nanocrystals and silicon nanocrystals were fabricated and characterized. Due to the formation of the quantum well in germanium due to the valance band energy offset between germanium and silicon, where holes are preferentially stored, both experiment characterization and simulation efforts suggested that germanium/silicon core-shell hetero-nanocrystal memory has a much better performance of retention, charge storage capability and operation speed than silicon nanocrystal memory. Second, ordered cobalt/aluminum oxide (Al2O3) core-shell nanocrystals aligned by using di-block co-polymer approach was used to further address the scalability of nanocrystal memory in terms of dot density variation. Compared with cobalt nanocrystal memory, cobalt/Al2O3 core-shell nanocrystal memory showed enhanced retention performance. Device simulations suggested that the enhancement is reasonable. These hetero-structured nanocrystals are promising for scaled nonvolatile memory device. Third, parallel aligned carbon nanotubes covered with Al2O3 were used as a template. Silicon nanocrystals were grown and aligned on the top of the ridges made by the carbon nanotubes. The growths were carried out using a homo-built gas source molecular beam epitaxy. The aligned nanocrystals were used as storage node and carbon nanotubes served as the field effect transistor memory channel after the device fabrication. Retention was measured as the change in drain current over time. Under linear extrapolation, the total charge retention of this device is observed to surpass 4×104 seconds, which is the longest retention measured for a carbon nanotube flash memory to date. Fourth, a nonplanar floating gate memory architecture with ultrahigh-density (∼1.5 × 1012 /cm2) nickel silicide nanocrystals as the floating gate is demonstrated using triangular-shaped silicon nanowire array as the transistor memory channel. The memory device showed large memory window, very good programming and erasing, long retention and high endurance characteristics. As conventional flash memory with a continuous floating gate faces increasing challenges and planar-type of devices are approaching scaling limit, this novel nonplanar device structure opens new possibilities for continuing nanocrystal memory scaling into future technology nodes. In terms of broader impact, first, three graduate students visited Nanjing University during the project to carry out the collaborative research. Detailed discussion of research on nonplanar nanocrystal floating gate memory devices and silicide nanocrystal memories was conducted. Graduate students from both sides worked closely on both experimental and theoretical simulation part of the project using Nanjing University’s advanced nanoscale device characterization facilities and existing simulation codes. The US students also visited a number of historic places in China. Second, the PIs and graduate students under the frame of this project worked with the San Bernardino Community College District to train the local workforce in the technician skills required to enter the field of nanotechnology. The courses taught were introductory to electronic and optoelectronic devices as well as fabrication and characterization techniques. Each training session included both lectures and hands-on training components and lasted 90 hours over a period of about 8 weeks. More than 370 trainees have completed the training so far. Third, during the engineering week each year, student clubs from the UCR College of Engineering held different events for the promotion of their particular fields. The PIs and their graduate students helped this effort by partnering with the student club of the society of Hispanic professional engineers (SHPE) to bring high school students from the local schools around the university to interact with the university students via some scientific activities. These events familiarized these high school students, many of these students are of low income Hispanic students with science and engineering concepts.
