The primary objective of this proposal is to demonstrate a scalable strained silicon technology that is integrated with advanced front-end processes. The scalability of the proposed approach is due to its applicability not only in planar bulk devices but also in a) strained silicon directly on oxide (SSOI) and in b) a novel double gate strained MOSFET (SSDG) that will be described in the proposal. The research will focus on strained Si layers since mobility enhancement can be obtained in both p-channel and n-channel devices. The program will consist of three research thrusts: a) Epitaxy of Strained Silicon layers, b) Advanced Gate stacks on Strained Silicon Layers and c) Device Demonstration. Since ITRS predicts the need for enhanced channel mobility by 2010, we believe initiation of this research effort in a timely manner is especially critical. The program is expected to stimulate innovation in development of alternative gate stack and junction processes suitable for strained layers. The program will take advantage of the diverse backgrounds of its investigators who have been working on advanced materials and processes for gate stacks, ultra-shallow junctions and low temperature epitaxy of Si and Si1-xGex alloys.
In the education and outreach activities, we plan to provide an enriching research experience for graduate students with emphasis on nanoscale materials and devices and establish a collaborative and interdisciplinary group research environment. We will also create a course on beyond planar devices for the graduate curriculum. Opportunities will also be provided for undergraduate students to get involved in the research through existing REU programs.
