This NIRT proposal focuses on the technology and underlying science for high-speed, low power, high-density Si-Ge-C planar and vertical Flash Electrically Erasable and Programmable Read Only Memories (EEPROMs) using high-k dielectrics and Si-Ge-C or metal Self Assembled Quantum Dot (SAQD) floating gates. Conventional flash EEPROMs have several serious drawbacks and this research investigates new memory cell structures with the goal of providing a compact, low-power, high-speed (programming, erase and read operation) semiconductor memory technology for future integrated circuit devices. The research will experimentally and theoretically explore: (1) the growth of ordered arrays of Si-Ge-C and metal nanoparticles on dielectric surfaces, employing chemical/physical vapor deposition (CVD or PVD) techniques that uncouple nucleation from growth. We will try to achieve high densities, spatial control and narrow particle size distributions, in concert with imprint lithography techniques; (2) development of high-k-based flash memory to allow for physically thicker, but electrically thinner "equivalent" oxides; (3) low band gap, high mobility Si-Ge-C heterolayers in the channel of planar flash cells to act as "cold cathodes"; (4) vertical nanoscale flash EEPROMs, which will allow bandgap engineering using Si-Ge-C along the channel; 5) first-principles modeling of nanoparticle structure evolution, including nucleation, growth, crystallization, and encapsulation within the dielectric to support experimental growth studies; and 6) theoretical modeling of hot carrier transport by hydrodynamic and Monte Carlo simulation, tunneling transport using transfer matrix methods, and quantum transport calculations of Coulomb blockade effects in the SAQDs. SAQDs enhance charge retention and VT stability, as well as possibly allow multi-level storage based on Coulomb blockade. High-k-based dielectrics should provide high capacitive coupling, without sacrificing non-volatility, and allow for lower-voltage and/or higher-speed operation through the potential-reduction in barrier height to channel hot electron (CHE) injection and tunneling, and increased device lifetime because of the thicker tunneling barriers under low field storage conditions. Si-Ge-C planar flash cells should enhance impact ionization and CHE, for reduction of operating voltages/powers and increasing programming speed. Vertical cell structures will allow the highest possible densities in a so-called cross-point architecture where the cell is located at the intersection of the wordline and bitline. The collaborative nature of the research will enhance the graduate student experience and develop team-building skills. The four graduate students will benefit from the joint supervision of the four co-PIs. Through this experience they will learn more about the areas outside their major area of study, and gain an appreciation of how other disciplines define problems and approach their solution. They will also get a chance to mentor under-grad students and get them excited with cutting-edge nanotechnology research. To bring the excitement of nanoscale objects and devices to the general public and to pre-college students, the co-investigators and their students will develop, produce and display exhibits that explain these revolutionary devices and their fabrication. The exhibits will be: used at local and regional science fun days and fairs; made available for display at regional K-12 schools and museums; and used in a traveling exhibit trailer that brings engineering awareness to underrepresented constituencies in Texas. We will have a strong industrial linkage with Dr. Bruce White, Manager of "Advanced Materials and Memories" at Motorola, Austin.
