The proposal requests funds to acquire and establish an Ultra-Fast pS RF-TLP Testing System Cluster for research on VDSM ICs down to nano-scale, including advanced super-GHz RF/mixed-signal ICs and on-chip ESD (electrostatic discharge) protection circuitry designs.
Intellectual Merits: ESD failure becomes a major IC reliability problem as semiconductor technologies move into VDSM ULSI regime. On-chip ESD protection circuitry is required to protect IC chips against ESD damage, while Super-GHz RF IC research is the foundation to future wireless communications where design and characterization of RF ICs is a big challenge. The PI has been conducting pioneering research on on-chip ESD protection and RF ICs sponsored by NSF and the industry, with several thrusts: 1. To investigate 3D mixed-mode ESD simulation approach. 2. To develop accurate high-current ESD device models. 3. To develop whole-chip ESD protection design verification CAD software. 4. To explore ESD protection solutions for sub-100nm ULSI ICs. 5. To investigate ESD phenomena and protection for future nano-scale technologies. 6. To explore ESD protection for super-GHz silicon RF ICs and emerging wide-bandgap GaN semiconductors. 7. To develop super-compact IC inductors for RF SoC. 8. To develop super-GHz ultra wideband (UWB) SoCs. 9. To develop 26GHz single-chip RFID SoC. 10. To develop high-performance ADC ICs. Advanced hi-f testing (<1ps) is critical to such research. The new Super-GHz RF-TLP Testing System Cluster consists of a Model 4012 CDM VSTLP Tester and a Model 11971B 8" RF Thermal Wafer Probing Station.
Broader Impacts: This new System will significantly enhance the research and teaching infrastructure at IIT. New courses and laboratories will be developed. Integrating diversity into research and teaching is planned. The facility will be open to inter-disciplinary research activities and external users to promote cross-disciplinary and university-industry collaboration on ESD protection and RF/mixed-signal ICs.
