The objective of this research is to develop a new clocking system for future-generation high-speed systems-on-chip such as high-performance multi-core microprocessors, in order to overcome the fundamental challenges in timing, noise and power consumption facing conventional clocking. In the proposed clocking scheme, a global clock is distributed across the chip, and then regenerated locally by injection-locked oscillators. The approach is based on a nonlinear circuit technique, injection locking, and a full suite of supporting technologies in systems, devices, and physics.
Intellectual Merit: This project will advance the understanding of timing uncertainties in integrated systems, investigate potential challenges in injection-locked clocking, and develop multi-level (device, circuit, and system) techniques to address both. The proposed clocking scheme can deliver significant power savings and noise reduction compared to conventional clocking, and seamlessly replace the latter without disruption to the design flow and manufacturing infrastructures.
Broader Impacts: The research results have the potential to critically impact computing, communications, radars, and other high-speed electronics applications. This project will enable a series of integrated educational activities through curriculum development, research results dissemination, and industry outreach. Special emphasis will be placed on under-represented minority student education and outreach to high school or younger students.
