The objective of this research is to advance the fundamental understanding of the benefits and limitations of using short-range, low-latency, wireless communications in a conventional, multichip computing environment. Traditional computing platforms, consisting of many integrated circuits on a single printed circuit board, incorporate several types of wireline interconnects with varying bandwidth and latency requirements. This research takes a holistic approach in exploring the implications of using short-range wireless communication on different levels of the computing system, from the circuits and communications to the networking and system architecture. These implications have the potential to pave the way to integrated designs and methodologies for incorporating wireless capability in the inter-chip communication infrastructure of next generation computing systems.
The intellectual merit of the research is the insight that the replacement of conventional, lower bandwidth serial communications with a multi-point, low-latency, wireless system will enable a number of computing system improvements, such as low latency, fault tolerance, reconfigurable bandwidth provisioning, and lower cost.
The broader impact of the research is the vertical involvement and co-design of the entire computing system platform, from the wireless circuits utilized in this system environment to the broadcast network protocols and system architectural implications. Potential benefits of this research include improving power consumption and fault tolerance in rack-mounted servers for cloud computing, as well as reducing cost and increased functionality in embedded applications such as future fourth generation cellular phones. With support from the GOALI industry partner, this project improves participation by students from underrepresented groups by active mentoring at the academic and industry partner locations.
