The objective of this research is to use the newly developed method of site-specific stamping for depositing graphene and few-layers graphene on a wide variety of substrates in making high-performance graphene-based devices. The approach is to first identify, design, and fabricate alternate substrates for enhanced device performance and functionality. Second, high-performance graphene devices are fabricated using the site-specific stamping method, in conjunction with atomic layer deposition of top gates. Third, direct current device characteristics, high frequency properties, and other device parameters are measured, analyzed, and correlated to the physical properties of the graphene layers. This research integrates experiment, theory, and atomistic modeling. The electronic properties within the graphene critically depend on the substrate, where carrier transport is limited by scattering and electron-phonon interactions. But the current choice of the substrate is largely restricted to silica and silicon carbide. The site-specific stamping method used here expands the choice of substrates, and has the potential to not only overcome some of the limitations but also allow engineering of carrier transport and band gaps in graphene. This is critical for the realization of high-performance graphene-based electronic devices. Current methods for graphene-based devices fabrication suffer from fundamental barriers: (i) not amenable to large-scale fabrication, (ii) lack of site-specificity in graphene placement, and (iii) severe restriction on substrates. The site-specific stamping method has the potential to overcome these critical barriers, and to make transformative contributions to high-performance graphene-based electronics. This research is used in enhancing classroom teaching and outreach experiences.
