The objective of this research is to investigate and create run-time adaptive error control methods for hybrid CMOS/nanoelectronics networks-on-chip. The approach is to exploit dynamic cooperation among layers in the on-chip network protocol stack, in order to adapt the error control to changing noise environments and achieve the required quality-of-service.
Intellectual Merit: This research addresses the critical reliability problem of integrating deep nanometer CMOS and emerging nanoelectronics processing and storage elements on a single chip. These dissimilar cores communicate with one another over closely spaced unreliable interconnect links, requiring effective error control methods to improve link reliability at moderate energy and performance costs. The research will (i) investigate, analyze, and construct run-time adaptive cooperative error control methods that adjust the error control to channel conditions for average-case, rather than worst-case energy performance; (ii) develop models that accurately capture realistic traffic and system behaviors of these unique hybrid networks-on-chip; and (iii) demonstrate a reliable heterogeneous network-on-chip prototype.
Broader Impacts: This project will accelerate realization of reliable low-cost energy-efficient heterogeneous systems-on-chip, potentially leading to societal and economic breakthroughs in biology, computing, communications, defense, and infrastructure monitoring. Knowledge acquired will be disseminated via workshops, lectures, and a public website. Further, the research will support development of a new course and the first textbook on the subject. Through the PI's already established community engagement and mentoring, this research will be used to inspire, recruit, and retain underrepresented students in engineering. Finally, ongoing international collaborations will enhance the research and global perspectives of US student participants.
