Intellectual Merit: This collaborative research project explores a scalable reconfigurable computing platform for Multimedia Signal Processing (MSP) applications using integrated two-dimensional volatile or non-volatile memory array as the primary computing element. The platform, referred to as Memory Based Multimedia Signal Processing (MBMSP), leverages on the fact that both nanoscale silicon as well as regular and periodic structures of many emerging nanoscale devices are amenable to dense, high-performance memory design. In MBMSP, algorithmic tasks are functionally decomposed into multi-input, multi-output functions, which are then mapped as lookup tables in a memory array and evaluated in a time-multiplexed, topological fashion using a small controller. This fundamentally different approach to information processing can be effective in developing a scalable platform with high-performance, reconfigurability, energy-efficiency and reliability for diverse and complex signal processing systems. The research seeks to develop circuit-µ-architecture-software co-design approach for MBMSP including software architecture to improve performance and scalability; circuit-µ-architecture techniques for memory cell and array to achieve low-power and robustness; software-hardware co-design approach for energy and reliability; and a Spin-Torque-Transfer Random Access Memory (STTRAM) based platform for scaling MBMSP to deep nanometer nodes.
Broader Impacts: The MBMSP platform can potentially transform the traditional approach to design multimedia signal processing system. The research will integrate education through course module development and undergraduate research projects. The teaching modules will be adapted for the local high-school students, including about 40% minority/under-represented students, who join the pre-college program at Case Western Reserve University every summer. The modules will focus on hands-on learning approaches for multimedia/digital signal processing systems and new ways to design them. PIs will continue their involvement with Facilitating Academic Careers in Engineering and Science for African-American (FACES) and Summer Undergraduate Research Experience for minorities (SURE). PIs will mentor one SURE student every summer and involve them in the proposed research.
The project has developed and studied a novel technology platform for computing with memory encompassing both hardware architecture and software tools. It has led to a novel reconfigurable computing hardware that exploits the properties of dense nanoscale memory to dramatically improve the energy-efficiency and operational reliability for diverse multimedia and signal processing applications. The proposed reconfigurable computing fabric advocates multi-cycle evaluations in each computational element by mapping function response, whenever possible, as multi-input/multi-output lookup tables in a dense two-dimensional memory array. The computing fabric has been evaluated with large set of benchmark applications and measurement of test-chips with the following key observations. 1) It significantly improves energy efficiency over state-of-the-art reconfigurable computing fabrics (e.g. Field Programmable Gate Arrays or FPGAs). 2) It is highly flexible – i.e. it can map diverse set of applications and support varying data type. 3) It has high technology scalability i.e. the advantages scale well in future technology nodes. 4) It is error-resilient and thus provides higher reliability of operation in advanced technologies. The memory-centric computing platform allows trading off between high performance (exploiting spatial parallelism) and low hardware requirement (exploiting time-multiplexing). Localized temporal evaluation drastically reduces the overhead due to the programmable interconnects, which greatly contributes to the energy and performance over traditional reconfigurable computing platforms. The circuit-architecture co-design has been pursued to improve the energy-efficiency of the proposed platform while ensuring reliable operation. The key innovation is to exploit the read-dominated access pattern of the memory-based computing platform. An static-random-access-memory (SRAM) array is designed that trades off performance of write operation for robust, low-power, and faster read operation. The integrity of the write operation, which occurs only during reconfiguration, is guaranteed by optimal voltage assists. A test chip has been designed and characterized to demonstrate the feasibility of memory-based logic blocks with the proposed circuit-architecture co-design. The application of non-CMOS technologies to further improve the hardware characteristics of the MBC platform has been studied for two technologies: (i) spin-torque-transfer-RAM and (ii) tunneling field-effect-transistors. The non-volatile nature of STTRAM improves the energy-efficiency while ultra-low-leakage TFET devices shows the potential of using MBC for very low power applications. With semiconductor industry predicting significant improvement in integration density for memory compared to logic gates in future technology generations, coupled with recent innovations in integration technology such as 3D integration, dramatic improvements in memory density, speed and power dissipation are expected in coming years. The proposed memory-centric reconfigurable computing platform can leverage on these benefits along with the non-volatility property of emerging nanoscale memory technologies such as molecular, resistive or spin-based memory. Another important benefit of using a memory array is that it can be dynamically configured into a custom logic or memory block, unlike alternative technologies. Such "malleable" nature can be extremely useful for other applications including many data-intensive applications, which benefit from improved memory latency and/or bandwidth. This feature significantly increases the applicability of the proposed computing paradigm beyond multimedia and signal processing tasks for which it has been evaluated. The proposed research contributed to curriculum development, teaching and training students. Three doctoral graduate students have been directly supported through this grant while two other graduate students have contributed. The students have learnt circuit design, performance/power simulation, different aspects of signal processing applications, and test-chip design/measurement.
