The objective of this research is to develop efficient millimeter-wave chip-to-chip data communications for multicore processors. The approach is to develop small CMOS compatible antennas for data transfers. The project involves design, analysis, and measurement of millimeter wave antennas on silicon and the interface electronics for on-chip communications. This includes electromagnetic modeling, circuit simulation and measurement on prototypes. Special antennas will be created to ensure minimal interaction between the antennas used for data transfers and the nearby CMOS circuitry used for processing.
The project's intellectual merits lie in its innovative approach to high-speed data transfers between integrated circuits in multicore computers. In processors with upwards of 100 cores, physical connections are complex and severely restrict performance. The use of the air-interface above the processors is a new concept for efficient data communications. High efficiency on-chip multi-antenna arrays will enable programmable direct processor-to-processor communications. The antenna links will increase data rates, conserve power, and consume an extremely small area.
The broader impacts of this research include potentially completely new computer architectures that enable fast computation of the world's largest problems, such as predictive models for severe weather forecasting. The research results will be used for a project for freshman college engineering courses and for elementary school demonstrations. Small low-profile antennas integrated onto Lego Mindstorms robots will be created so that the robots can communicate to one another wirelessly. Creation of this hands-on project is expected to improve recruitment and retention of a diversity of students in engineering.
The semiconductor industry has learned how to build multiple processors (called cores) on integrated circuits. This is done in order to split the computations between the multiple processors on the IC and save energy by turning off unused processors. Also, computations (wifi, apps, audio, etc) for PCs, tablets and cellphones can be performed in parallel at slower speeds by "low voltage" cores which also saves energy. The older way of doing computations was to perform all the work with one high speed high voltage processor (core) which consumed much more energy. The physics of this situation shows that there is substantial energy savings per computation which drastically increases the performance and energy efficiency of our portable modern computational devices. Thus, allowing extended many hour battery operation. With the industry selling microprocessors with to eight and more cores, a new performance bottleneck comes about, the cores cannot move data to each other fast enough. To maintain good user experience, it is imperative that cores communicate at high speed and that high speed data paths can be established to enable fast core-to-core data transfer. Wireless techniques can provide this data transfer but it is necessary to minimize the circuit complexity. Also, it is necessary to minimize the area and the power consumption of the wireless circuits and to maximize the antenna efficiency. It is desirable to employ simpler wireless circuits that use the same frequency rather than use multiple frequencies. This collaborative University of Florida research work with University of Arizona demonstrates three features necessary for the ultimate integration of wireless transmitters and receivers into many core (multi-core) microprocessor systems. These features are 1) Low power circuits for high speed data transmission across an array of cores, 2) differential techniques which enable signal selection from adjacent antennas and 3) extremely efficient on-chip or nearby IC package antennas approaching 90% efficiency from the University of Arizona. The research highlights in this University of Florida work are the differential antenna systems and the demonstrations of extremely low power circuits for transmission of signals in microprocessor cores. The research has demonstrated unique compact antennas on a circuit board in which selected nearby antennas received much stronger signals at a given frequency. This was accomplished by using differential signals that feed the energy to the antennas. These differential signal can be changed on the fly while operating these antennas. This allows the circuits to select which direction the antennas strongly broadcast. This research result can be used in designs for small microprocessor on-chip antennas, high efficiency antennas and for 60 GHz package antennas. In particular, For 90° angular offset, an isolation of 30 dB was observed in a close differential antenna system which was nearly 8 dB more when compared to that of single ended system. A simulation of the antenna system at 5cm/20cm vertical/horizontal separation revealed a 16 dB extra isolation achieved by the differential system over single ended system. The antenna sizes and geometries were not optimized for on-chip communications in these results and there are great opportunities to improve on-chip antenna isolation with further research. The researchers demonstrated the use of CMOS technology for compact low power transmission and reception of data signals on-chip. These transceiver designs are compatible with a multi-core microprocessor system. The chips show how to build a new communication channel between processor cores beyond the wired communications that currently exist on the microprocessor. This demonstrated new communication channel is very high speed allowing 2 billion computer bits per second (2 Gb/s) of data to be moved between cores per channel. By making multiple wireless channels on the IC and using more advanced technology 50 Gb/s to 100 Gb/s of extra communications can be achieved in a multi-core microprocessor. These links can greatly speed up the performance of the multi-core microprocessor. In particular, the designs achieve a 6 pJ/bit energy consumption and are implemented at 15 GHz on 130nm CMOS Technology and simulations of 90nm CMOS showed 60 GHz operations. The transmitter power will be reduced drastically if the design is ported to a more modern, low power and low capacitance 45nm or 28nm CMOS RF technology.
