The objective of the proposed research program is to study scaled charge-trap nonvolatile semiconductor memory (NVSM) and CMOS devices. Our study will focus on two hetero-insulator device structures: (1) metal and polysilicon gate, high-K, nanoscaled CMOS transistors with fixed charge in the high-K dielectric and (2) a nonvolatile, charge-trap, nanoscaled SINOS semiconductor memory device with programmable charge storage. In particular, we will focus on the quantum mechanical modeling and experimental characterization of carrier mobility degradation due to remote Coulomb and surface roughness scattering, charge transport and trapping and gate leakage in high-K CMOS devices. The charge trap NVSM devices are SINOSlike structures with a gate dielectric comprised of a tunnel oxide (O), a storage silicon nitride (N), and an overlying high-K blocking oxide (I) as aluminum oxide and/or hafnium dioxide to increase the dielectric constant of the film. We will fabricate and model experimental scaled 5V SINOS devices with an emphasis on Write/Erase, Retention and Endurance and study the influence of stored charge in the nitride on the carrier mobility. We have developed a novel technique to extract the low-field carrier mobility with a two-terminal C-V and G-V measurement to permit the optimization of the hetero-insulator gate dielectric. The SINOS devices offer a unique opportunity to electrically place charge near the Si-SiO2 interface and to explore their influence on carrier mobility. We will examine 1/f and RTS noise in these devices with a focus on unifying existing theories through a consideration of both trapped and free charge fluctuations. We will complement the electrical characterization with material measurements on film thicknesses and compositions, especially in the use of atomic layer deposition (ALD). In addition, we will employ high-resolution transmission electron microcopy (HRTEM) and angle-resolved X-ray photo spectroscopy (ARXP) to study film thickness and structural properties and their relation to theoretical models.
The intellectual merit relies on an integration of research and education to explore low-field, carrier transport in charge-trap NVSM and high-K nanoscaled CMOS devices with a quantum mechanical treatment of mobility degradation, charge trapping, gate leakage, and low-frequency RTS and 1/f noise. We examine mobility with a simple two-terminal conductance/capacitance measurement to minimize the need to fabricate complete three-terminal devices with ohmic contacts until an optimized gate stack has been determined in the experiments. NVSM devices offer a unique approach to electrically locate and position charge centers in the vicinity of the Si-SiO2 interface to study their influence on carrier transport and storage as well as gate leakage and low-frequency noise. Our theoretical and experimental studies will be complemented with a variation of material parameters and the use of advanced materials characterization techniques with HRTEM and ARXPS to model nanoscaled NVSM and CMOS devices. The broader aspects in our program will advance diversity in the nanoelectronics workforce and provide intellectual technology transfer, integration of research and education, and promotion of partnerships with the industrial sector of the economy. We have developed excellent educational and outreach programs to increase diversity with opportunities in nanoelectronics, especially silicon semiconductor devices an important area to maintain US leadership and provide jobs for graduates in a global silicon-based semiconductor industry. Our research offers an excellent vehicle for minority student outreach, internships, and partnerships with industry. The transformative nature of our research lies in (1) a new approach to obtain low voltage, low power dissipation NVSMs with alternate high-K films to maintain barrier height while increasing the dielectric constant, (2) a new, quantum mechanical 1/f noise model, and (3) a novel method to model low field transport with simple two-terminal C-V and G-V structures, which is easily fabricated without extensive photolithographic equipment. The concept is applicable to the study of carrier transport in a broad range of emerging nanoscaled devices, not necessarily silicon, and will aid rapid and innovative advances in the field of semiconductor technology.
