Wireless communication chips with lower power consumption are needed to enable more widespread wireless connectivity for numerous battery-powered portable and implantable biosignal measurement devices. However, reduced power consumptions lead to degraded performance and reliability, which inhibits the adoption of low-power circuit design approaches. Innovative integrated circuit design techniques are required to alleviate this tradeoff in medical applications, wireless sensor networks and chips with energy harvesting features. The primary research objective of this project is to create design methodologies for performance and reliability enhancements of tunable low-power analog circuits through the incorporation of efficient digital circuits. A key educational goal is to pioneer a unified approach through which students collaboratively learn to combine low-power analog integrated circuit design and digitally assisted performance tuning methods with a primary focus on cutting-edge medical applications. New course materials will establish a long-lasting research and education program aimed at creating reliable wireless capabilities for various miniaturized devices. Undergraduates and high school interns will be directly involved in research tasks. The project team will collaborate with Northeastern University's Center for STEM Education to organize on-campus activities with K-12 students and teachers as well as outreach visits to connect with underrepresented groups in local schools.
State-of-the-art low-power receivers are prone to interference due to their limited dynamic ranges, which is particularly severe when multiple wireless medical monitoring devices coexist in close proximity to each other. To overcome this challenge, an adaptive design methodology will be devised to enhance interference suppression through extra filtering in the receiver path. This research effort will address the performance deficiencies of low-power integrated circuits such that a broader range of devices can be equipped with short-range wireless connectivity. It will provide new knowledge to design transceivers with better immunity to interference through the introduction of adaptive filtering in RF front-ends, digitally assisted linearity improvements for low-power analog circuits, and digital spectrum analysis for self-calibrations. Novel circuit-level linearization methods will be demonstrated to enable the design of analog circuits that include transistors operating in the subthreshold region with substantially improved dynamic ranges. These methods will be leveraged to achieve leading-edge performance with less than one-sixth of the power compared to current transceivers. The research will produce techniques to evaluate gain and linearity characteristics of analog circuits using an efficient fast Fourier transform engine that calculates the frequency spectrum of signals with significantly less chip area than existing methods. This will be a foundation for new built-in test and calibration strategies that counteract rising process variations of advanced chip manufacturing technologies.
