Every aspect of modern life (e.g., economy, health, and communication) is dependent on advanced electronics. As such, discovering methods that improve the performance of electronic systems will directly lead to improvements in quality of life. Moreover, improving the energy efficiency of electronics directly impacts society as it reduces the carbon footprint of modern data centers and increases the lifetime of ubiquitous mobile devices. This project aims to improve both the performance and energy efficiency of electronic systems by exploring a new electronic integration concept based on heterogeneous interconnect stitching. The principle innovation in the proposed integration approach is the use of stitch chips on the surface of a package to form dense and low-energy interconnects between the assembled dice. The assembled chips, moreover, are interconnected using multi-height and multi-pitch compressible micro-interconnects, which are high density mechanically flexible interconnects that enable robust interconnection between all chips. To accomplish our objectives, the following fundamental research topics are investigated: 1) analysis of the power supply noise in multi-die assemblies using interconnect stitching; 2) experimentally demonstrating the assembly of a 2x2 array of chips using interconnect stitching; and 3) extracting the frequency-dependent parasitics of the compressible micro-interconnects up to 50 GHz. All research will be performed at Georgia Tech, which is one of the nodes within the NSF supported National Nanotechnology Coordinated Infrastructure program. This enables us to easily expose K-12 students to this research and encourage them to pursue science and engineering education. The proposed research will also involve the graduate and undergraduate students conducting the research with multiple disciplines that include electrical engineering, mechanical engineering, and chemical engineering. Such research experience will enhance their education and better prepares students to work in industry because they would already have a fundamental understanding of how different disciplines interact with each other in electronic systems.
The performance and power dissipation of electronic computing systems have become increasingly dominated by interconnections. The proposed Heterogeneous Interconnect Stitching Technology (HIST) can greatly reduce interconnect length between components; thereby offering higher bandwidth density at reduced energy per bit. Moreover, the proposed research will enable the integration of active devices (photonic, logic, memory, etc.) in very close proximity (i.e., face-to-face bonding); thereby greatly reducing electrical parasitics and improving interconnect densities. But, the proposed integration approach may exacerbate the challenges in power delivery due to increased power density of the assembled package. As a result, the intellectual merit of the proposed research is twofold. First, the proposed research will develop fundamental understanding of the power delivery network design in the proposed heterogeneous integration approach to minimize parasitics-induced voltage drops and switching noise as a function of several technology parameters. Second, the proposed research will experimentally demonstrate the key interconnect and assembly technologies that will enable low-power and high-performance computing systems. The experimental effort will specifically focus on developing a 2x2 array of dice interconnected using stitch chips and the characterization of the HIST interconnect channels up to 50 GHz. The experimental research will also explore robust and high-yield batch-scale fabrication of multi-height and multi-pitch compressible micro-interconnects as well as their mechanical reliability.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
