The primary objective of the proposed research is to produce an accurate model of trap generation and leakage currents to develop effective models of breakdown and to maintain a certain level of performance as the dimensions of nonvolatile memory transistors are scaled. The research strategy involves parallel efforts on trap state generation, annealing of stress-induced damage, and the development of a theoretical analysis utilizing second order trapping kinetics theory for the analysis of key phenomena which are characteristic of dielectric breakdown failures.
