The presence of harmonics in power systems has become a matter of increasing concern in recent years. The development of power electronic devices and the resulting use of power converters in the system load have greatly increased the level of harmonic currents being injected into the system. The goal of this work is to develop methods for determining capacitor bank location and sizing so as to reduce the system impedance at the significant harmonics. The methods used are pole-zero analysis and input-output analysis to determine the effects of capacitor placements on eigenvalue sensitivities or gain sensitivities.
