Complimentary metal oxide silicon (CMOS) static random access memory (SRAM) cells have decreased in size more than two times with the introduction of each new generation of SRAM array. Now the transient effects of excess carrier generation on the circuits of the memory cell must be understood in order to design the SRAM cells. The research is to design an equivalent circuit model of an SRAM cell which approximates the cell transient response during a single event upset. The model will be verified both numerically and experimentally. Applications to the design of SRAM arrays will be investigated.
