This project supports collaborative research by Dr. Mahmoud Wagdy, Department of Electrical Engineering, California State University-Long Beach. The Egyptian collaborator is Dr. Hamed El-Simary at the Electronics Research Institute, Cairo, Egypt. They plan to investigate a novel flash fast locking wide-band Digital Phase-Locked Loop (DPLL). There are many applications (communications, industrial, etc.) which significantly influence information technology insofar as speed and throughput are concerned. These applications are Radio Frequency (RF) ones in the GHz frequency range, and thus require fast-locking digital phase-locked loops (DPLLs). The research will provide a working novel fast-locking DPLL in the GHz range (> 2 GHz) using 0.18 microm CMOS process, which is cheaper than other technologies such as SiGe, Bipolar, etc. The project objectives include: (1) a comparative study of various categories of fast-locking DPLLs employing: a mathematical algorithm to achieve fast convergence, nonlinear characteristics for the CP (charge pump) to change the convergence rate, feedback with the CP and PFD (phase frequency detector), or current-mode techniques; the existing literature includes tens of papers and patents, not thousands as in conventional DPLLs; the study will employ behavioral modeling tools such as Simulink, Verilog and/or VHDL, (2) designing (using Cadence/Mentor Graphics) the proposed novel fast-locking DPLL comprising two stages: a coarse-tuning stage based on a flash (parallel) algorithm, followed by fine-tuning stage similar to conventional DPLLs, (3) timing analysis to assess advantages over other techniques, derivation of closed-form formulae for lock time using actual hardware delays, as well as lock time analysis via behavioral modeling, (4) reduction of the following: lock time, frequency overshoot, phase noise (jitter), spurious signals, and static noise errors due to mismatches in PFD/CP, (5) investigating DPLL stability (via Simulink), parasitic awareness, RF issues (via Agilent ADS software), etc., and (6) fabrication, and hardware testing. Intellectual Merit: This research will fill a number of voids in the relatively recent field of digital fast-locking phase-locked loops. It will provide more complete understanding of the differences between various categories of these DPLLs via mathematical and behavioral modeling techniques. In particular, the research will provide a complete quantitative basis including closed-form formulae, for computation of the lock time, which is a critical performance parameter for many important applications. The proposal presents a novel wide-band DPLL using a flash algorithm, which is conceptually similar to the one employed by flash A/D converters; this algorithm is the counterpart of the slower successive-approximation algorithm employed by many fast-locking DPLLs. Broader Impacts: Because of the need for fast-locking DPLLs for cellular phones, spread-spectrum communications, information technology, and clock/data recovery (CDR) circuits, this research will benefit private industry, space agencies, and the society at large. The project will support graduate students for working on this international cooperative project. This project is being supported under the US-Egypt Joint Fund Program, which provides grants to scientists and engineers in both countries to carry out these cooperative activities.
