This Small Business Innovation Research Phase I project will develop a theoretical and experimental proof-of-concept, along with instrumentation and technique, for non-contact, in-line resistance measurement of nanostructures (transistors, interconnects, contacts, via, etc.), required to improve the process yield of today's integrated circuit (IC) chips. Conventional methods for the electrical characterization of microcircuits focus on test structures that use dedicated test wafers. Measurements are performed post fabrication with predefined landing pads that consume valuable silicon real estate. The data obtained from the dedicated wafer are used for product wafer characterization and yield estimation; however, such data are not necessarily accurate for IC chip design on product wafers. This project involves developing a next generation electrical test (e-test) technique, for non-contact interconnects capacitance (C) measurement, without the need for probe pads, using MEMS-based piezoelectric nanoprobes that are self-activating and self-sensing.
This test system for non-contact R and C measurement will revolutionize the microcircuit e-test characterization. The innovations proposed herein include the in-line non-contact e-test technique for R measurement, and (along with C measurement) on-the-fly determination of such interconnect process parameters as line width (top and bottom), wire thickness, and trapezoidal shape of the copper interconnect under test. These interconnect process parameters can be used for back end IC process characterization and monitoring to ensure the process is running within specs.
