This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).
This Small Business Technology Transfer (STTR) Phase II research project will develop and apply a principled design methodology to confront the serious problems associated with deep sub-micron, system-on-chip, integrated-circuit designs. The project will develop design services for companies wishing to market complex, proprietary, low-power integrated circuits through the development of a unique design tool, one which will apply a mathematically sound approach to the production of large, hazard-free, network-on-chip products. The goal for this tool is to reduce traditional design cycles by eliminating most of the global verification effort while improving the robustness of the design. New results in predicting the behavior of deep submicron arbiter circuits are essential to this work and will also be reported.
The broader impacts of this research are to reduce design costs, time-to-market and power consumption. More broadly this can: 1) significantly increase the productivity of integrated-circuit design engineers, 2) reduce power consumption of electronic control, communication and computational systems and 3) increase our competitiveness against off-shore system-on-chip designers particularly with respect to low volume products. Thus, successful completion of this project is important to the future of the national electronics marketplace because, without a major reduction in the time spent on global verification, the benefits of higher levels of integration, including reductions in time-to-market, conservation of power and increases in reliability, will not be available to many important electronics market sectors.
(Award 0924010) Many wondrous electronic products have been developed in the last few decades. Examples are mobile phone, portable tablets, remote sensors and implanted medical devices. All these products and many others are made possible by integrated circuits popularly know as "computer chips." Every year the semiconductor industry turns out billions of tiny bits of silicon and every year each new chip is more powerful than in years before. A recently introduced chip, no bigger than a fingernail, now contains as many as 20 billion transistors. That is about three transistors for every man, woman and child on the earth, all packed on a single, tiny chip. Two important challenges, scalability and reliability, confront continued progress in the design and production of each new generation of chips: Scalability is the property that allows the semiconductor industry to produce significantly less expensive transistors in every succeeding generation. Scalability must also exist in the tools that enable design engineers to manage the complexity of increasingly dense System-on-Chip (SoC) products. Reliability is the property that minimizes chip failures despite the steady growth in their complexity. This is a significant challenge because doubling the number of transistors on a chip every two-year generation means more opportunities for failure. As a result individual transistor failure rates must be significantly reduced from one generation to the next. Designers of contemporary SoCs must divide their work into hundreds of independent domains to manage the enormous complexity of these devices. This complexity can be compared with that of the world's 7-billion people living in 200 different countries. The independent domains of each SoC operate on different clocks and serve different computational functions, but must communicate with each other across their domain boundaries. This is analogous to the countries of the world operating in different time zones and doing business in different languages. Just as trouble often arises at the boundaries between countries, trouble also arises as information travels from one clock domain to another. In fact, the clock-domain-crossing problem has been widely recognized as an increasing source of design difficulty and product unreliability. The scalability and reliability challenges mentioned above are inexorably linked and must be solved together. Blendics has addressed these two challenges with its two major technologies: DANI is a Delay-tolerant Asynchronous Network Interface. This silicon intellectual property (IP) is a patented technology for interconnecting independently clocked domains. DANI eliminates the need for a global clock tree and for absolute timing constraints on clock domain crossings. DANI supports independent clock domains and relative timing constraints. MetaACE is an analysis tool for assessing the reliability of clock domain crossings. This EDA tool will become essential as safety-critical applications of computers proliferate and clock-domain crossings grow in number to many hundreds on a single chip. Mean-time-between-failures (MTBF) is a popular measure of reliability. An MTBF exceeding a million years is required for any SoC that performs advanced safety features in an automobile in volume production. MetaACE can give that assurance to the automotive manufacturer and the public. With NSF support two important milestones have been reached for these Blendics products. The DANI technology is being licensed to a financial services provider as an essential component of a high-performance trading system. Without DANI the components of this trading system cannot be made to work together at the required speed. This is true even using the advanced design software provided by the FPGA vendor. Thus, DANI has demonstrated the advantages of an asynchronous network-on-chip in a complex, high-performance design, a design that could not meet timing constraints with the best contemporary EDA tools. MetaACE is being marketed as both a free, down-loadable tool for educational purposes and as a premium service that semiconductor vendors can use to verify the MTBF of their SoC products. The free version has been installed at four universities (Washington University, Southern Illinois University Edwardsville, University of Southern California and The Technion, Israel) with many more universities to come. The first sale of the premium service has been recently completed to an international semiconductor manufacturer. The results obtained from MetaACE have been validated by comparison with measurements in silicon. Two conference papers have been published and a journal paper is in press. These papers describe the validation of MetaACE, some new results for multistage synchronizers and an analysis of the deleterious effects on reliability introduced by increases in variability of transistor threshold voltages. As a result of NSF support, Blendics has been able to develop, introduce and market two new products that help to address the dual challenges of scalability and reliability facing the semiconductor industry. In addition the free version of MetaACE will help to train engineers throughout the world in the management of an important digital system reliability problem.
