This Small Business Innovation Research (SBIR) Phase I project investigates a novel epitaxial process that simultaneously grows and transfers epitaxial structures from a semiconductor substrate to an assembly substrate. It addresses a number of fundamental barriers persist to mass production and commercialization of compound semiconductor devices namely: 1)material cost, 2) substrate size, 3) component/subsystem integration, and 4) thermal issue. Among the cost drivers, the crystalline substrate and epitaxial layer typically account for more than half of the finished wafer cost. Depending on the type of materials for each application, wafer sizes vary widely. The resulting barrier is a lack of a technology platform (fabrication and integration platforms either monolithic or modular) versatile enough to intermix and integrate devices made from different materials that allow higher performance and/or functionality. In most high performance devices, there is a need for lower the thermal resistance between device?s active layer and heat sink. The project goals are to demonstrate feasibility for manufacturing by demonstrating clear advantages over conventional methods in providing low cost, high quality, and low thermal resistance epitaxial materials. Unlike prior art layer transfer techniques, this method provides high yield and streamlines package and assembly steps by eliminating some processing steps.
The broader impact/commercial potential of this project will be to enable wide applications, especially in defense, space, and commercial sectors. Using our innovative method, the contact area of epitaxial layer to crystalline substrate is reduced and epitaxial growth volume (both vertical and lateral overgrowth) is defined by a patterned assembly substrate. The reduced contact area enables a highyield layer transfer process. The assembly substrate standardizes substrate size for further processing regardless of the original material sizes. The epitaxial layer transferred directly onto an assembly substrate provides a unit building block for higher level of device and subsystem integration. These applications and devices include but not limited to optoelectronics such as lasers, sensors, optical data storage, fiber optics, light emitting diodes (LED), and photovoltaics (PV), radio frequency (RF) and wireless systems, and microwave, millimeterwave, radar, and satellite communication systems. For commercialization of our solution, our target customers are manufacturers of photonic components that require highyield layer transfer, fast heat transfer at semiconductor device level, and integrability of different materials for high performance. The addressable market in manufacturing of photonic and communication components is estimated to be over $30 billion.
NSF 09-541 IC4E SBIR Phase I Project: EPITAXY-LEVEL PACKAGING What is the intellectual merit of the proposed activity? 1. This Small Business Innovation Research will provide a unique fabrication and integration platform for compound semiconductor with silicon or other materials. This platform provides the ability to mix different semiconductors onto a common substrate that is engineered for cost reduction of devices. During Phase I we demonstrated proof of concept of epitaxy-level packaging (ELP) in a novel epitaxial layer growth and transfer scheme. The objectives for Phase II are to 1) develop a methodology to evaluate material systems for ELP implementation, 2) mature ELP technique and deliver an ELP wafer prototype to end user(s), and 3) design production tooling for ELP wafer production. The research plan includes development of equipment to achieve multiple material growths of epitaxial islands on a common substrate; demonstration and characterization of growths using said equipment; characterization of key growth parameters enabling use of a common substrate; and development of a reliable separation method. These will together result in the design of cost-effective production tool that can be used by already identified strategic partners. Our focus in Phase II is to develop an ELP process and ELP wafer specifications by partnering with industry-leading compound semiconductor wafer fabs and integrated device manufacturers. What are the broader impacts of the proposed activity? 2. The broader impacts are to provide an enabling technology for cost effective integration and manufacturing of compound semiconductor devices now used in optoelectronic, radio frequency (RF), and related industries. This is accomplished by device integration at the earliest stage of fabrication using a technology that does not yet exist. This technology is expected to reduce overall device footprint because of this early integration, furthering the trend towards miniaturization in a diverse set of both commercial and defense applications that include lasers, sensors, detectors, imaging devices, LEDs, RF/microwave/millimeter-wave integrated circuits, photovoltaic cells, power electronics, and thermoelectric generators. The technology described in this proposal will lead to material-based platform for compound semiconductors on which cost-effective device fabrication and integration with silicon can be built on a single standard. For example, substrate size currently varies for different materials due to manufacturing constraints. Successful completion of the goals of the project will provide understanding in the interrelated parameters for growth via epitaxy within constrained features. 3. Key words: compound semiconductor, epitaxial growth, epitaxial layer transfer, epitaxy-level packaging, hybrid integration
