This Small Business Innovation Research (SBIR) Phase I project seeks to develop a novel memory, which has both volatile and non-volatile functionality. Such memory combines the non-volatile memory?s ability to retain information in the absence of power (such as Flash memory) and the fast access speed and reliability of a volatile memory (such as Static Random Access Memory (SRAM)). This memory is fabricated using a mainstream or near-production fabrication process and is a one-transistor device, which results in a compact cell size, suitable for cost-efficient high density applications. The proposed memory cell integrates a floating body transistor and a phase change memory element. During normal operation, the memory device functions as a floating body memory device and has SRAM-like performance, as in the access speed, power, and endurance capability. When power is removed from the memory device, the state of the floating body is saved into the phase change memory element by means of a mass, parallel, self-feedback mechanism. Subsequent to power restore, the original state of the floating body is recovered, also by means of a mass, parallel, self-feedback mechanism.
The broader impact/commercial potential of this project is to enable power-efficient computing applications and mobile devices. For example, it can be used to reduce power consumptions in data centers. Data centers? annual energy consumption is estimated to be 150 billion kWh, about twice the capacity of the current US solar panel. A power-efficient memory such as the one proposed in this proposal can reduce the overall data centers? power consumption by up to 75%. Another application is to provide an integrated memory solution. Many electronic devices currently employ multiple types of memory, due to their own distinct characteristics. The proposed device will be able to combine the different types of memory into a single memory device.
This Small Business Innovation Research (SBIR) Phase I project seeks to develop a novel memory, which has both volatile and non-volatile functionality. Such memory combines the non-volatile memory’s ability to retain information in the absence of power (such as Flash memory) and the fast access speed and reliability of a volatile memory (such as Static Random Access Memory (SRAM)). This memory is fabricated using a mainstream or near-production fabrication process and is a one-transistor device, which results in a compact cell size, suitable for cost-efficient high density applications. During normal operation, the memory device functions as a floating body memory device and has SRAM-like performance, as in the access speed, power, and endurance capability. When power is removed from the memory device, the state of the floating body is saved into the phase change memory element by means of a mass, parallel, self-feedback mechanism. Subsequent to power restore, the original state of the floating body is recovered, also by means of a mass, parallel, self-feedback mechanism. The broader impact/commercial potential of this project is to enable power-efficient computing applications and mobile devices. For example, it can be used to reduce power consumptions in data centers. Data centers’ annual energy consumption is estimated to be 150 billion kWh, about twice the capacity of the current US solar panel. A power-efficient memory such as the one proposed in this proposal can reduce the overall data centers’ power consumption by up to 75%. Another application is to provide an integrated memory solution. Many electronic devices currently employ multiple types of memory, due to their own distinct characteristics. The proposed device will be able to combine the different types of memory into a single memory device. Through collaboration with Stanford University, we have successfully fabricated a proof-of-concept of the novel memory device. A single cell test structure and a 4×4 mini array have been fabricated at Stanford Nanofabrication Facility (SNF), followed by its electrical characterization. The device characteristics in both volatile and non-volatile modes have been investigated, where the volatile mode shows a bi-stable nature that allows for potential SRAM applications. In addition, TCAD simulations are also performed to understand the mechanism of the device operation. A publication describing the memory device as well as an analysis of the underlying mechanism has been submitted. Challenges related to the relatively large amount of current to write the non-volatile elements have been identified. These challenges are related to the large device size fabricated in this work. We seek to resolve this challenge through collaboration with partners that can provide us access to more advanced fabrication capability.
