This Small Business Innovation Research Phase I project proposes an on-demand verification (ODV) facility for analog / mixed-signal application (A/MS) specific integrated circuits (ASICs). The technology innovation is a virtualized cloud-based verification platform that supports all aspects of A/MS ASIC verification for integrated circuit design centers, including behavioral modeling, test bench management, simulation planning, simulation farming, and data mining. The proposed ODV system scales with ASIC complexity and design staff expansion by leveraging cloud computing resources. More importantly, the proposed verification resources can be scaled down once verification tasks are complete, creating opportunities for small design centers to create high quality designs with competitive cost structure for design operations. The initial proof-of-concept design system will be equipped with open source EDA design, modeling, and verification software tools. The modularity inherent in the proposed verification platform will also support the installation of best-in-class commercial partner software solutions and their use in ASIC verification activities by subscribers to the ODV facility.

The broader impact/commercial potential of this project is to improve the competitiveness of U.S. semiconductor industry by reducing A/MS design verification cycle time, improving first pass design success and reducing time-to-market. The complexity of A/MS ASIC design has aggressively followed Moore?s law, but innovations in design verification have not. Small, fabless analog design centers in particular struggle to compete in complex design creation given the existing EDA licensing model. Equipping a small design team with the proper verification and analysis tools, for example, is financially equivalent to quadrupling the staff. The results of this research work will lower barriers to entry and innovation for small and emerging companies by providing a scalable verification service without the onerous burden of additional software licensing costs and infrastructure overhead. In addition, the ODV system enables more collaborative innovation among the market players through a cloud-based platform. This would materially benefit the existing semiconductor market participants and open the door for new participants.

Project Report

" This Small Business Innovation Research Phase I project proposed the prototype development of an On-Demand Verification (ODV) system for analog/mixed-signal (A/MS) integrated circuit development through a cloud-based platform that allows collaboration. Verification of today’s complex integrated circuits and systems is widely acknowledged as a critical challenge to improving design productivity. The proposed ODV system called ZipODVTM supports critical aspects of A/MS integrated circuit verification including behavioral modeling, test bench creation and management, simulation planning, simulation farming, and data management. The prototype implemented during the Phase I research validates the critical concepts that demonstrate feasibility for this approach. Phase IB extended this effort and established additional intellectual property necessary for commercialization. The broader impact of the completed ODV system resulting from this research is to improve the competitiveness of the U.S. semiconductor industry by reducing A/MS design verification cycle time, improving first-pass design success, and reducing time-to-market. The results of this research work will lower barriers to entry and innovation for small and emerging companies by providing a scalable verification service while minimizing software and hardware infrastructure costs and support burden. Furthermore, the ODV system enables more collaborative innovation among the market players through a cloud-based platform. The prototype developed during the first six months of the SBIR Phase I grant and subsequent six month SBIR Phase IB grant demonstrates that the primary technical objectives for this product are feasible and create a strong foundation for commercialization. Several elements of the resulting architecture are patentable: one patent application has been filed, and a second is almost complete. Nine additional patentable ideas resulting from this research have been identified. Early components of the prototype have been leveraged in three verification services engagements with a major U.S. based global semiconductor company. The initial successful engagement created revenue that enabled the Phase IB extension for the ODV program. Efforts will now move to development of a commercial product offering.

Project Start
Project End
Budget Start
2012-07-01
Budget End
2013-06-30
Support Year
Fiscal Year
2012
Total Cost
$174,250
Indirect Cost
Name
Zipalog, Inc.
Department
Type
DUNS #
City
Plano
State
TX
Country
United States
Zip Code
75074