This Small Business Innovation Research (SBIR) Phase I project proposes an analog verification coverage system. Today well-accepted formal and simulation-based techniques exist to capture and measure test coverage for digital integrated circuits, but there is no corresponding commercial capability for analog integrated circuits. Analog designers frequently spend much time analyzing and over-testing system behavior for a small set of well understood usage scenarios while leaving significant portions of the state-space completely untested. The design exploration problem for analog circuits presents critical challenges for implementing such a system due to the inherently large design space typical of analog circuits. The proposed innovative solution addresses this issue by determining the design space of relevance for a specific circuit and then assessing the completeness of exploration for that identified area. A prototype set of instruments will be delivered that measure coverage during analog/mixed-signal simulations. The proposed product will automatically parse the design netlist, add the instrumentation, run the user's existing simulator, analyze the output from the instrumentation, save data to a database, and build a coverage profile. This capability provides improved productivity and quality of results by eliminating redundant simulations and identifying areas of the design space that have not been sufficiently tested.
The broader impact/commercial potential of this project is to improve the competitiveness of U.S. semiconductor industry by improving the quality of A/MS design verification, improving first pass design success and reducing time-to-market. The complexity of A/MS ASIC design has aggressively followed Moore's law, but innovations in design verification have not. More importantly the ideas being developed through this project have broader implications for complex systems that cross the boundaries between multiple domains and do not conform well to the highly constrained verification methods used for digital circuits. Multiple domain verification problems include integrated circuits used in combination with micro-electromechanical or opto-electronic devices, integrated circuits that are utilized in complex environments such as biomedical applications, as well as integrated circuits that are delivered in innovative forms rather than traditional packages where the verification of the entire delivery system is critical. Examples would include chips mounted directly on flexible substrates or contained within multi-chip modules that may include stacked die. To enable broad accessibility to small businesses as well as dispersed efforts such as geographically distributed design teams or research efforts, this capability can be delivered through an on-demand verification infrastructure being developed as part of an earlier project.
This Small Business Innovation Research Phase I project proposed the prototype development of an analog verification coverage system for analog/mixed-signal (A/MS) integrated circuit development. Verification of today’s complex integrated circuits and systems is widely acknowledged as a critical challenge to improving design productivity. Part of the verification challenge revolves around understanding what portion of the operating space has been examined; i.e., "covered". Today well-accepted formal and simulation-based techniques exist to capture and measure test coverage for digital integrated circuits, but there is no corresponding commercial capability for analog and mixed-signal integrated circuits. Analog designers frequently spend much time analyzing and over-testing system behavior for a small set of well understood usage scenarios while leaving significant portions of the state-space completely untested. The design exploration problem for analog circuits presents critical challenges for implementing such a system due to the inherently large design space typical of analog circuits. The proposed innovative solution ZipCovTM addresses this issue by determining the design space of relevance for a specific circuit and then assessing the completeness of exploration for that identified area. A prototype set of "instruments" implemented during the Phase I research measure coverage during analog simulations. The prototype automatically parses the design netlist, adds the instrumentation, runs the user’s existing simulator, analyzes the output from the instrumentation, saves data to a database, and builds a coverage profile. This capability provides improved productivity and quality of results by eliminating redundant simulations and identifying areas of the design space that have not been sufficiently tested. This prototype validates the critical concepts that demonstrate feasibility for this approach and meets the objectives from the initial proposal. A critical open question addressed by the prototype was demonstrating that simulation performance was increased by less than 20% compared to throughput without the coverage instrumentation. This initial research developed unique intellectual property (IP) with six patentable ideas identified. The strong patent position will provide good protection for a commercial product. A critical missing element to the hybrid top-down/bottoms-up analog behavioral modeling and transistor level simulation strategies in use today is the inability to assess the quality and coverage of the verification plan. No capability exists on the market today to measure analog coverage. The prototype developed during this project is a viable step to address this missing link. ZipCov can ensure that a transistor-level implementation of a circuit has been exercised under all the conditions and scenarios applied to the macro-model in the top/system-level simulations. A basic example of this capability was demonstrated with the prototype. With the completion of a successful prototype and performance metrics that achieved the stated objectives, efforts will now move to development of a commercial product based on the key technology incorporated in the prototype.
