This Small Business Innovation Research Phase I project advances a novel method to fabricate 3D IC interconnects. Physical and economical limitations for 2D scaling (Moore's Law) prevents further increase of integration density to improve the performance of integrated circuits (IC). These challenges have stimulated the development of 3D through-silicon via (TSV) technology (so called 'More than Moore') in order to increase the speed and the bandwidth of the devices as well as to decrease the form factor and power consumption of integrated microsystems. However, the implementation of 3D TSV technology is limited by the high cost of 3D TSV fill (due to the use of expensive vapor deposition and chemical-mechanical processes) and its poor scalability (due to low conformality of physical and chemical vapor deposited films) to high TSV aspect ratios and smaller via sizes (to increase I/O). The objective of this investigation is to address this problem in order to enable cost-effective and reliable fill of high aspect ratio 3D TSVs. This goal will be achieved with the use of novel electrochemical materials and processes enabling conformal anodic isolation and electroless barrier/seed films, as well as selective electrochemical Cu TSV filling.
The broader impact/commercial potential of this project will be to accelerate the mass-scale adoption of low cost and scalable TSV technology in semiconductor manufacturing. The development of 3D TSV packaging is carried out by various companies in USA, Europe, Japan, Korea, Taiwan, etc. However, the high cost and low scalability 3D TSV filling process prevents mass-adoption of 3D IC interconnects. Our proprietary low-cost, scalable and selective (electrochemical TSV fill technology will allow us to decrease the cost of TSV fill technology by a factor of > 2 and to increase the scalability by a factor of > 3 to fabricate low cost, high speed, large bandwidth and broader functionality 3D devices. Therefore, the successful completion of this project would not only have a significant societal impact by accelerating 3D IC wafer technology adoption into state-of-art high performance digital devices such as next generation of smart phones, but also have positive economic impact by creating US semiconductor jobs and maintaining US technology leadership over a wide range of semiconductor applications.
. Physical and economical limitations for 2D scaling (so called "Moore’s Law") prevent further increase of integration density to improve the performance of integrated circuits (IC). These challenges have stimulated the development of 3D through-silicon via (TSV) technology (so called "More than Moore") in order to increase the speed and bandwidth of the devices as well as to decrease the form factor and power consumption of integrated microsystems. However, the implementation of 3D TSV technology is limited by the high cost of 3D TSV fill (due to the use of expensive vapor deposition and chemical-mechanical processes) and its poor scalability (due to low conformality of physical and chemical vapor deposited films) to high aspect ratios and smaller via sizes (to increase I/O). NANO3D selective electrochemical metallization process technology (LOCOS) developed during Phase I project addressed cost and scalability issues of 3D interconnect technology by replacing costly vapor deposition processes and eliminating chemical-mechanical process with cost-effective low temperature selective electrochemical processes for selective TSV metal fill and redistribution layer formation (RDL). LOCOS technology includes the following major process steps such as a) selective activation with uniform adhesion/catalytical layer containing <30 nm thick (photosensitive or self-assembled) film functionalized with Pd or Au sub-10 nm nano-particles, b) low temperature electroless deposition of conformal CoWP or NiWP barrier layers that is continuous down to 10 nm thickness and with good barrier properties against Cu diffusion up to 500 OC followed by c) low temperature electroless Cu deposition of predominantly (111) texture to selectively fill TSV down to 5 μm and form RDL with Cu patterns down to 5 μm width. This will enable to replace costly vapor deposition and chemical-mechanical processing as well as damascene technology to make redistribution layers and fill the TSV's. The feasibility of LOCOS technology for TSV fill and RDL formation was demonstrated on 3D TSV test structures with potential to reduce the cost by over 2X and increase the scalability by over 3X for volume production of 3D IC’s. The broader impact/commercial potential of this project will be to accelerate the mass-scale adoption of selective electrochemical metallization technology to lower the cost and increase the scalability of 3D interconnects. NANO3D proprietary low-cost, scalable and selective electrochemical TSV fill technology will allow customers to decrease the cost of TSV fill technology and to increase the scalability in order to fabricate low cost, high speed, large bandwidth and broader functionality 3D microsystems including heterogeneous integrated systems for next generation smart phones and other communication devices.
