The broader/commercial impacts of this this Small Business Innovation Research (SBIR) Phase I project are both technical and economic. The developed error-correction solutions will enable flash-memory-based devices to have higher capacities, higher reliability, and faster speeds at lower power while driving down the cost. This will have a major impact on mobile computing capabilities and enterprise storage by improving the efficiency and reliability of data centers, servers, and mission-critical storage that incorporate flash memories. Improved enterprise storage boosts the efficiency and growth of IT businesses, e-commerce, and financial trade. The solutions will also enable reduced power consumption and heat dissipation leading to greener systems, which is also a key driver for increased economic growth. From 2000 through 2012, the U.S. GDP has increased by 23.12% while energy consumption from all sources has increased by only 3.88% and this trend will be reinforced. The benefits of the error-correction solutions are also applicable to the hard disk drive and communications industries involving hundreds of billions of dollars in revenue and double digit growth rates.
This Small Business Innovation Research Phase 1 project is related to the development of novel low-density parity-check (LDPC)-based error-correction for flash memory-based solid state drives (SSDs). While SSDs are rapidly gaining prominence especially in enterprise storage due to their high speeds, low power, and low heat dissipation, they face a major scaling problem as flash memory cell sizes must be shrunk to reduce their high cost, leading to an unavoidable degradation in the reliability. With a trend of increasing die density to enable higher storage capacities, more powerful error-correction is required. Therefore, the industry is swiftly moving towards adopting LDPC codes which can provide greater error-correction than the currently used codes. However, LDPC codes have a high decoding complexity and suffer from the error floor problem which prevents them from achieving very low error-rates needed in storage. Existing LDPC solutions use complex post-processing to deal with the error floor problem at the cost of more power and hardware making them unattractive for next generation SSDs. Using a unique design approach based on the analysis of iterative decoder failures, new LDPC solutions will be developed and validated on hardware that will achieve the target reliability enhancements needed for emerging memories, with a reduction of 10-20% in hardware and power compared to state-of-the art solutions. They will be optimized specifically to meet the reliability needs of enterprise SSD.
Solid state drives (SSDs), which are based on flash memory technology (traditionally used in USB sticks and SD cards), have now emerged as the medium of storage for both consumer devices such as tablets and laptops (e.g. MacBook Air) as well as larger enterprise storage systems such as servers and datacenters. The main reasons are that, unlike conventional hard-disk drives (HDDs), they do not contain any movable parts leading to more durability, less power, and less heating dissipation, while providing much faster read/write speeds. However, SSDs cost much higher than HDDs. In order to reduce cost and enable higher storage capacities, flash memory manufacturers have been shrinking the memory cell sizes and storing more data (per cell). Every SSD contains a flash controller chip which is completely responsible for managing the read/write process of data on the flash memory. One of the critical components of the flash controller chip is the error-correction algorithm employed by the chip to maintain reliability in the stored data by correcting any errors introduced due to various phenomenon associated with the physics of flash memories. More errors are introduced with repeated cycles of writing and over-writing data on the flash memory and therefore the maximum number of such cycles until which the device can perform reliably is the lifetime or endurance of the device. Error-correction involves encoding the data by adding some redundancy in a prescribed manner before writing it so that when the error-prone data is read and decoded, errors are corrected. The flash memory industry’s drive to reduce the cost by shrinking the memory cell sizes along with the trend to increase storage capacities lead to an unavoidable degradation in the endurance of the device, and the burden to maintain the desired reliability falls on the error-correction used in the flash controller chip. Due to this, the industry is quickly moving towards the adoption of a modern class of error-correction codes known as Low-density Parity-Check (LDPC) codes which can offer much greater error-correction capability compared to previously used codes. However, current LDPC-based error-correction codes still have two main issues:1) their decoders are too complex in hardware and use too much power which are not suitable for consumer devices, and 2) their decoders drastically reduce the read speed when enhanced reliability is required which is not acceptable for enterprise storage systems that require extremely fast speeds. With emerging storage applications requiring even greater speeds, enhanced reliability, and even lower power usage, current LDPC-based error-correction codes are insufficient to meet the needs of next-generation SSDs. Codelucida is developing novel LDPC-based error-correction using a unique design approach that can achieve greater reliability and increased speeds along with savings in power compared to state-of-the-art making it attractive for both consumer and enterprise SSD applications. Through the SBIR Phase-1 project, we were able to develop new LDPC-based error-correction algorithms that were implemented and validated for certain code parameters on field programmable gate array (FPGA) boards, which are hardware boards with programmable circuitry to implement the algorithms. The main outcomes of the project include 1) the design of new LDPC codes for certain code parameters suitable for flash memories, 2) the design and development of novel decoders for the codes, 3) development of initial FPGA prototypes of the new LDPC decoders, and 4) comparison of performance with state-of-the-art LDPC decoders on the same FPGA platform. The results obtained from the hardware illustrated that our new decoders can provide 1-2 orders of improvement in reliability along with nearly 50% savings in chip area and power, and increased speeds compared to state-of-the-art. The next step in our development is to extend the designs to a wider range of code parameters used in flash controllers, and further develop a prototype that can be incorporated and tested on real data from a flash memory system.
