The broader impact/commercial potential of this Partnerships for Innovation - Research Partnerships (PFI-RP) project is to develop and commercialize the technologies to create the next generation hardware for microcontrollers (a type of computer chip). The market of the microcontroller-based devices has been rapidly growing and expected to continue, thanks to recent trends such as the Internet of Things (IoT), wearables, smart buildings, mobile robots, drones, etc. This market has been seeking microcontroller hardware that consumes very little power to extend the battery life. This market also has been seeking to increase computing capability to meet the growing need of complex workloads, such as a neural network algorithm, without much-increasing power consumption. However, since they were first developed multiple decades ago, microcontrollers have undergone rather incremental improvements and cannot support those emerging needs. The proposed technology, if successful, will create next-generation microcontroller hardware to achieve significantly higher performance, power-efficiency, and robustness, thereby supporting this critical market demand and posing a strong value proposition.
The proposed project will further develop several recent NSF-funded research results. The near- and sub-threshold voltage (NTV, STV) techniques, where the supply voltage is scaled down to a half to a quarter of the nominal level, has been considered one of the most effective ways to reduce power consumption. However, this approach has not been widely accepted because the hardware quickly loses robustness across operating conditions (temperature), manufacturing process variations, and long-term device aging. This problem becomes even worse with non-Von-Neumann hardware accelerators and analog-mixed-signal building blocks in the microcontroller system-on-chip. This project's objective is to create and commercialize the technologies that can effectively address the robustness challenge and thus achieve one to two orders of magnitude better power-efficiency and performance. The proposed effort in this project will be centered on creating power/area-efficient in-situ error detection and correction circuits (EDAC) and on-chip integrated digital voltage regulators and DC-DC converters that are applicable for commercial microcontrollers, non-Von-Neumann neural-network accelerators, and analog-mixed-signal building blocks. The anticipated result of the project is the silicon prototype of the next-generation microcontroller hardware integrating the developed technologies, demonstrating largely improved performance, power, and robustness.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
