This project is to investigate the feasibility of using a commercially available digital signal processor chip as a high performance coprocessor to perform statistical computations at speeds approaching that of lower end supercomputers. Initially, the building blocks necessary for statistical computation will be selected. From these building blocks, optimized algorithms and hardware/software configurations for this chip use will be determined based on analytical, simulation, and experimental results. The ultimate goal is a flexible, interactive, high- speed, and low-cost statistical workstation capable of solving a wide range of complex statistical problems. There are potential commercial applications in research laboratories, commercial enterprises, universities, and other areas where economical high-speed statistical computing is needed.
