Real-time recognition of speaker-independent connected speech has proven to be a difficult problem for electronic systems. Low-precision highly-parallel analog neural networks have been shown to recognize speaker-dependent small- vocabulary connected speech using standard components. This project will research and develop massively-parallel custom integrated circuits that will perform this task, using integrated delay lines and analog computing networks. Phase I will include the design and fabrication of test chips to prove the feasibility of our development. The approach will utilize standard readily available CMOS Bulk integrated circuit technology so products arising from this research can be fabricated reliably and economically by a number of vendors. The P.I. has already demonstrated using this technology to fabricate continuous-time analog computing networks and non-linear decision circuits. He have also shown the feasibility of using floating-nodes to provide non-volatile storage of analog voltages. These voltages can be used to control the operation of the chip thus implementing the capability to learn or be trained in the field. This proposed research addresses the challenging and important problem of real-time speech recognition and may lead directly to inexpensive products with wide commercial applicability.
