This project is the design and fabrication of a high-performance convolver integrated circuit that can be coupled to a digital neural network classifier. The architecture has a predicted single-chip performance of 50 billion multiply/accumulates per second, which can be maintained with realistic chip I/O bandwidths. The high performance is achieved at the architecture level by computing several convolution kernels simultaneously, and at the circuit level by using compact multiplying DAO's and analog current summing. The prototype designed during this project will be fabricated using commercial bulk CMOS technology.
