This research investigates the functional behavior and VLSI realization of a novel, scalable and intelligent wafer-level communications network (the Silicon Wafer Area Network or SWAN) supporting fine grained communications with predictable network traversal times. The network's "intelligence" is chosen to adaptively and dynamically establish virtual interconnections with the functionality of direct point-to-point interconnections for passage of individual messages through the network. The network is assumed to be a wafer-level function, allowing highly parallel data links between switches by exploiting the high density of IC wiring. The network organization is similar to a systolic processing array, using nearest neighbor connections and pipelined data movement through the network to establish high data rates. The critical issue of load balancing is based on (1) achieving sufficiently high communications rate capabilities so that network links are sparsely used (i.e. a rate capability well in excess of the required data rates) and (2) a global routing and load balancing algorithm based on electrostatic and potential energies (i.e. a network "activity potential"). The distributed computations of the potential energies provides each local node with a slowly varying measure of link usage in regions away from that node. The specific research completes VLSI design and circuit simulations of the performance of the network nodes. In addition, the research develops a network simulator to investigate the steady state and transient behavior of the network with various routing and load balancing algorithms selected to achieve the maximum VLSI area/speed performance.