This project proposes to develop a receiver system for high-speed MRI. This novel system will integrate a digital receiver with reconfigurable real-time processors in order to receive MR signals and process image in real time during an MRI experiment. The receiver system will be built on a single integrated-circuits (IC) chip of a Field Programmable Gate Array (FPGA). The architecture of the receiver will include developed modules for the analog RF front end, digital baseband signal demodulation, receive control, in-line data correction and image reconstruction. By taking advantage of the parallel processing capability of FPGAs, the receiver will not only control the multiple processing modules running simultaneously, but also allow real-time inter-module interactions. This capability will enable high-speed MRI and offers the potential for expansion to true dynamic stabilization of the system hardware in the future work. We describe a research plan for the design, construction and testing of all individual modules, for the integration of these modules into a functional receiver system prototype, and for incorporating this system into our Bruker 9.4T MRI scanner. The architecture of the receiver will be implemented on a commercially-available FPGA board and thus the design approach will be easily be shared with other research labs in MRI community. We anticipate that integrating the proposed receiver with an MRI scanner will offer a cost-efficient, flexible tool for achieving high-speed imaging and suppressing data errors induced by system perturbations. This system will be particularly valuable for a variety of applications in the fields of functional and connectivity neuroimaging using MRI.
We propose to develop a prototype multi-channel receiver for Magnetic Resonance Imaging (MRI). The receiver will consist of a digital signal demodulator integrated with reconfigurable real-time processors. It will be built on a single-chip Field Programmable Gate Array (FPGA). A distinct feature of this integrated receiver is that it will be capable of acquiring MR signals and processing images on a single device. We expect that with the integrated receiver incorporated into our existing MRI scanner, we will be able to achieve high-speed imaging and suppressing statistical errors in image data induced by system perturbations.
| Li, Limin; Wyrwicz, Alice M (2018) Parallel 2D FFT implementation on FPGA suitable for real-time MR image processing. Rev Sci Instrum 89:093706 |
