This collaborative research focuses on the physical layer of digital communication system design ? in particular on the analysis, design, and implementation of capacity-approaching low-density parity-check (LDPC) codes for practical communication environments. In the last ten years, the area of channel coding has undergone a revolutionary change with the growing popularity of graph-based codes and iterative decoding algorithms. These coding methods, which include both turbo codes and LDPC codes, approach the limits of channel coding performance promised by Shannon in his landmark 1948 paper. Currently, these codes are in the process of replacing conventional error control techniques in numerous digital communication and storage standards, including, among others, deep-space communication, next-generation wireless transmission, last-mile cable transmission, digital video broadcasting, and high-density digital magnetic recording.
The research addresses several issues related to graph-based codes. In particular, it focuses on the analysis, design, and implementation of LDPC convolutional codes, which have several advantages compared to LDPC block codes, but have not received much attention from the research community. Conventional convolutional codes, on the other hand, have had a transformative effect in numerous practical communication environments, and the same is likely to be true in the capacity-approaching world of LDPC codes. The project emphasizes bridging the gap between advanced theoretical research and realistic practical implementations. In particular, it is concerned with adapting LDPC convolutional code designs to various industry standards that require flexibility in both frame length and code rate and with developing VLSI implementations of hardware decoders that can be tested under real operating conditions.
