Dr. Ciesielski is investigating methods for optimizing signal path delays and clock skew in VLSI circuits, with the aim of improving VLSI chip performance. Specifically, the goal of this research is to find efficient techniques for adjusting, or fine tuning, wiring delays in VLSI chips at the lowest level of physical design. This will be accomplished by assigning conducting layers to interconnect wires and placing contacts (vias) at layer changes. A model for the minimization of critical path delays is proposed, in which precise RC characteristics of interconnect wires and vias are taken into account. This model will be extended to incorporate other objectives in the optimization of interconnect delay, such as the minimization of clock skew, equalization of data path delays and introduction of precisely controlled wire delays in data paths.
