Although gate matrix and functional array layout styles have received much research attention, algorithms for these methods are not complete enough to assess their design potential. The P.I. is developing a complete VLSI module generation system based on these design styles and performing a thorough evaluation of them. The system takes many design issues into consideration: transistor sizing, timing analysis, physical-sized (gridless) routing and layout, array folding, array partitioning, and variations on the gate matrix layout. Research work includes: a new representation for dynamic nets, new recursive min-cut algorithms, algorithms for performing net assignment in NMOS and CMOS independently, a five-stage algorithm for compaction, a graph representation for functional arrays, and algorithms for layout generation, transistor reordering and traversing a reduced graph. A complete study of these two layout styles is being performed, and the results evaluated against standard design methods, such as standard cell. New VLSI design styles need to be developed in order to design complex, high transistor count IC's. This research investigates two new design styles, gate matrix and functional array layout methods. The P.I.'s approach is unique in that he intends to answer the basic question of whether these promising design styles are better than traditional approaches. The novelty is in the concepts to be used in building a design system that completely covers the design problem. The principal investigator is a promising and competent young professor who should make significant contributions to the field.
